Soumya Banerjee

Affiliations:
  • University of Illinois at Chicago, Department of Electrical and Computer Engineering, IL, USA


According to our database1, Soumya Banerjee authored at least 7 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
The existence of universally agreed fairest semi-matchings in any given bipartite graph.
Theor. Comput. Sci., 2020

2017
A General Design Framework for Sparse Parallel Prefix Adders.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A local reconfiguration based scalable fault tolerant many-processor array.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
An STT-MRAM based strong PUF.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A general approach for highly defect tolerant Parallel Prefix Adder design.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013
Decentralized self-balancing systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013


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