Soumika Majumder

According to our database, Soumika Majumder authored at least 2 papers in 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process.

Soumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang

Proceedings of the 21st International SoC Design Conference, 2024

A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process.

Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024