Sotirios G. Ziavras

IET Wirel. Sens. Syst., 2016

Wireless sensor network-based infrastructure damage detection constrained by energy consumption.

[BibT_eX]

[DOI]

William Contreras

Proceedings of the 7th IEEE Annual Ubiquitous Computing, 2016

Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration.

[BibT_eX]

[DOI]

Yaojie Lu

Seyed Amin Rooholamin

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Performance-Energy Optimizations for Shared Vector Accelerators in Multicores.

[BibT_eX]

[DOI]

Khondaker Musfakus Salehin

IEEE Trans. Computers, 2015

A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines.

[BibT_eX]

[DOI]

IEEE Syst. J., 2015

Modular vector processor architecture targeting at data-level parallelism.

[BibT_eX]

[DOI]

Seyed A. Rooholamin

Microprocess. Microsystems, 2015

A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies.

[BibT_eX]

[DOI]

Int. J. Comput. Sci. Eng., 2015

2014

ASIC Design of Shared Vector Accelerators for Multicore Processors.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013

Multicore-based vector coprocessor sharing for performance and energy gains.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Efficient on-chip vector processing for multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on System on Chip, 2013

Packet classification using rule caching.

[BibT_eX]

[DOI]

Nitesh B. Guinde

Proceedings of the 4th International Conference on Information, 2013

FPGA and ASIC square root designs for high performance and power efficiency.

[BibT_eX]

[DOI]

Shashank Suresh

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm.

[BibT_eX]

[DOI]

Imtiaz Sajid

Muhammad Mansoor Ahmed

J. Signal Process. Syst., 2012

Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Versatile design of shared vector coprocessors for multicores.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Message from General Chairs.

[BibT_eX]

[DOI]

Ioannis Vlahava

Proceedings of the IEEE 24th International Conference on Tools with Artificial Intelligence, 2012

2011

On-chip Vector Coprocessor Sharing for Multicores.

[BibT_eX]

[DOI]

Proceedings of the 19th International Euromicro Conference on Parallel, 2011

2010

Online anonymity protection in computer-mediated communication.

[BibT_eX]

[DOI]

Sara Motahari

Quentin Jones

IEEE Trans. Inf. Forensics Secur., 2010

Scheduling for input-queued packet switches by a re-configurable parallel match evaluator.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2010

Efficient hardware support for pattern matching in network intrusion detection.

[BibT_eX]

[DOI]

Nitesh B. Guinde

Comput. Secur., 2010

Novel FPGA-Based Signature Matching for Deep Packet Inspection.

[BibT_eX]

[DOI]

Nitesh B. Guinde

Proceedings of the Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010

FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization.

[BibT_eX]

Imtiaz Sajid

Muhammad Mansoor Ahmed

Proceedings of the VISAPP 2010 - Proceedings of the Fifth International Conference on Computer Vision Theory and Applications, Angers, France, May 17-21, 2010, 2010

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance.

[BibT_eX]

[DOI]

Imtiaz Sajid

Muhammad Mansoor Ahmed

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

On the Exploitation of Narrow-Width Values for Improving Register File Reliability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Customized kernel execution on reconfigurable hardware for embedded applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2009

Designing for different levels of social inference risk.

[BibT_eX]

[DOI]

Sara Motahari

Quentin Jones

Proceedings of the 5th Symposium on Usable Privacy and Security, 2009

Preventing Unwanted Social Inferences with Classification Tree Analysis.

[BibT_eX]

[DOI]

Sara Motahari

Quentin Jones

Proceedings of the ICTAI 2009, 2009

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

Identity Inference as a Privacy Risk in Computer-Mediated Communication.

[BibT_eX]

[DOI]

Proceedings of the 42st Hawaii International International Conference on Systems Science (HICSS-42 2009), 2009

Exploiting narrow-width values for thermal-aware register file designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Social Inference Risk Modeling in Mobile and Social Applications.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008

Robust scalability analysis and SPM case studies.

[BibT_eX]

[DOI]

J. Supercomput., 2008

Self-Adaptive Data Caches for Soft-Error Reliability.

[BibT_eX]

[DOI]

Constantine N. Manikopoulos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Asymmetrically banked value-aware register files for low-energy and high-performance.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior .

[BibT_eX]

[DOI]

Xin Tang

Int. J. Netw. Secur., 2008

BTB Access Filtering: A Low Energy and High Performance Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Partially Reconfigurable Vector Processor for Embedded Applications.

[BibT_eX]

[DOI]

J. Comput., 2007

Coprocessor design to support MPI primitives in configurable multiprocessors.

[BibT_eX]

[DOI]

Alexandros V. Gerbessiotis

Rohan Bafna

Integr., 2007

Reconfiguration support for vector operations.

[BibT_eX]

[DOI]

Hongyan Yang

Int. J. High Perform. Syst. Archit., 2007

FPGA-based Vector Processing for Matrix Operations.

[BibT_eX]

[DOI]

Hongyan Yang

Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Runtime Partial Reconfiguration for Embedded Vector Processors.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Vector Processing Support for FPGA-Oriented High Performance Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Asymmetrically Banked Value-Aware Register Files.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Study of Data Exchange Protocols for the Grid Computing Environment.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Measuring Network Parameters with Hardware Support.

[BibT_eX]

[DOI]

Kanchan Devarakonda

Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Resource management for dynamically-challenged reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007

Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors.

[BibT_eX]

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005

Modeling distributed data representation and its effect on parallel data accesses.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2005

FPGA-based vector processor for algebraic equation solvers.

[BibT_eX]

[DOI]

Hongyan Yang

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A hierarchically-controlled SIMD machine for 2D DCT on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Optimizing the Thermal Behavior of Subarrayed Data Caches.

[BibT_eX]

[DOI]

Johnsy K. John

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Load-balanced CICB packet switch with support for long round-trip times.

[BibT_eX]

[DOI]

Ziqian Dong

Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

FPGA-Based Vector Processing for Solving Sparse Sets of Equations.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method.

[BibT_eX]

[DOI]

Tae-Gyu Chang

Proceedings of the Embedded and Ubiquitous Computing, 2005

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2004

FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture.

[BibT_eX]

[DOI]

Satchidanand G. Haridas

Parallel Algorithms Appl., 2004

A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2004

A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Processor design based on dataflow concurrency.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2003

Viable Architectures for High-Performance Computing.

[BibT_eX]

[DOI]

Paraskevi Papathanasiou

Comput. J., 2003

Parallel Direct Solution of Linear Equations on FPGA-Based Machines.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Load Balancing on PC Clusters with the Super-Programming Model.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 2003

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines.

[BibT_eX]

Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003

2002

Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs).

[BibT_eX]

[DOI]

Segreen Ingersoll

Microprocess. Microsystems, 2002

2001

A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers.

[BibT_eX]

[DOI]

Taras I. Golota

VLSI Design, 2001

2000

A new-generation parallel computer and its performance evaluation.

[BibT_eX]

[DOI]

Haim Grebel

Anthony T. Chronopoulos

Florent Marcelli

Future Gener. Comput. Syst., 2000

Versatile Processor Design for Efficiency and High Performance.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

1999

Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing.

[BibT_eX]

[DOI]

VLSI Design, 1999

Evaluating the communications capabilities of the generalized hypercube interconnection network.

[BibT_eX]

[DOI]

Sanjay Krishnamurthy

Concurr. Pract. Exp., 1999

Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Network Embedding Techniques for a New Class of Feasible Parallel Architectures.

[BibT_eX]

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998

Robust interprocessor connections for very-high performance.

[BibT_eX]

[DOI]

Proceedings of the Robust Communication Networks: Interconnection and Survivability, 1998

1997

Parallel generation of adaptive multiresolution structures for image processing.

[BibT_eX]

[DOI]

Xi Li

Constantine N. Manikopoulos

Concurr. Pract. Exp., 1997

1996

Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer.

[BibT_eX]

[DOI]

Arup Mukherjee

Parallel Comput., 1996

Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture.

[BibT_eX]

[DOI]

Xi Li

Constantine N. Manikopoulos

Concurr. Pract. Exp., 1996

Performance Analysis for an Important Class of Parallel-Processing Networks.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Parallel Architectures, 1996

1995

Scalable Multifolded Hypercubes for versatile Parallel Computers.

[BibT_eX]

[DOI]

Parallel Process. Lett., 1995

Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers.

[BibT_eX]

[DOI]

Michalis A. Sideras

Int. J. Pattern Recognit. Artif. Intell., 1995

1994

RH: A Versatile Family of Reduced Hypercube Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1994

Adaptive Multiresolution Structures for Image Processing on Parallel Computers.

[BibT_eX]

[DOI]

Peter Meer

J. Parallel Distributed Comput., 1994

High-performance emulation of hierarchical structures on hypercube supercomputers.

[BibT_eX]

[DOI]

Devenkumar P. Shah

Concurr. Pract. Exp., 1994

A class of scalable architectures for high-performance, cost-effective parallel computing.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

Generalized reduced hypercube interconnection networks for massively parallel computers.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994

1993

Efficient Mapping Algorithms for a Class of Hierarchical Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1993

Connected component labelling on the BLITZEN massively parallel processor.

[BibT_eX]

[DOI]

Image Vis. Comput., 1993

Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study.

[BibT_eX]

[DOI]

Muhammad A. Siddiqui

Concurr. Pract. Exp., 1993

1992

On the Problem of Expanding Hypercube-Based Systems.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1992

Processor Allocation for a Class of Hypercube-Like Supercomputers.

[BibT_eX]

[DOI]

Nagasimha G. Haravu

Proceedings of the Proceedings Supercomputing '92, 1992

Connection Machine Results for Pyramid Embedding Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Parallel Processing: CONPAR 92, 1992

1990

Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems.

[BibT_eX]

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989

On the mapping problem for multi-level systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

1988

Improved algorithms for translation of pictures represented by leaf codes.

[BibT_eX]

[DOI]

Nikitas A. Alexandridis

Image Vis. Comput., 1988

1986

Architectural Adaptations for Hierarchical Image Processing/Transmission.

[BibT_eX]

Nikitas A. Alexandridis