Sorin A. Huss

Affiliations:
  • Darmstadt University of Technology, Germany


According to our database1, Sorin A. Huss authored at least 114 papers between 1982 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2020
Nested genetic algorithm for highly reliable and efficient embedded system design.
Des. Autom. Embed. Syst., 2020

2016
An Efficient Approach to Anonymous Distribution of ITS Messages in Geographic Areas via LTE and IRS Networks.
Proceedings of the Information Systems Security and Privacy, 2016

An Anonymous Geocast Scheme for ITS Applications.
Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016

Attribute-based authorization tickets for Car-to-X communication.
Proceedings of the 2016 IEEE Conference on Communications and Network Security, 2016

2015
Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes.
ACM Trans. Reconfigurable Technol. Syst., 2015

A Web-Based Visualization and Animation Platform for Digital Logic Design.
IEEE Trans. Learn. Technol., 2015

Real-world evaluation of an anonymous authenticated key agreement protocol for vehicular ad-hoc networks.
Proceedings of the 11th IEEE International Conference on Wireless and Mobile Computing, 2015

Path Hiding for Privacy Enhancement in Vehicular Ad-Hoc Networks.
Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

An Efficient Anonymous Authenticated Key Agreement Protocol for Vehicular Ad-Hoc Networks Based on Ring Signatures and the Elliptic Curve Integrated Encryption Scheme.
Proceedings of the Information Systems Security and Privacy, 2015

A Novel Anonymous Authenticated Key Agreement Protocol for Vehicular Ad Hoc Networks.
Proceedings of the ICISSP 2015, 2015

2013
MARV-X: Applying Maneuver Assessment for Reliable Verification of Car-to-X Mobility Data.
IEEE Trans. Intell. Transp. Syst., 2013

A generic, scalable reconfiguration infrastructure for sensor networks functionality adaption.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Novel Techniques to Handle Rectangular Areas in Car-to-X Communication Applications.
Proceedings of the ICINCO 2013 - Proceedings of the 10th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Reykjavík, Iceland, 29, 2013

A Methodology for Invasive Programming on Virtualizable Embedded MPSoC Architectures.
Proceedings of the International Conference on Computational Science, 2013

AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework.
Proceedings of the Number Theory and Cryptography, 2013

2012
A Novel Framework for Efficient Mobility Data Verification in Vehicular Ad-hoc Networks.
Int. J. Intell. Transp. Syst. Res., 2012

Hardware virtualization-driven software task switching in reconfigurable multi-processor system-on-chip architectures.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

On Clock Frequency Effects in Side Channel Attacks of Symmetric Block Ciphers.
Proceedings of the 5th International Conference on New Technologies, 2012

Predictive maneuver evaluation for enhancement of Car-to-X mobility data.
Proceedings of the 2012 IEEE Intelligent Vehicles Symposium, 2012

A Novel Analysis Method for Assessing the Side-Channel Resistance of Cryptosystems.
Proceedings of the Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2012

A General Approach to Power Trace Alignment for the Assessment of Side-Channel Resistance of Hardened Cryptosystems.
Proceedings of the Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2012

An adaptable, modular, and autonomous side-channel vulnerability evaluator.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Side-channel resistant AES architecture utilizing randomized composite field representations.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Bil: A tool-chain for bitstream reverse-engineering.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation Specifications.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Side channel analysis of the SHA-3 finalists.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

On the Design of Hardware Building Blocks for Modern Lattice-Based Encryption Schemes.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

An adaptive system architecture for mitigating asymmetric cryptography weaknesses on TPMs.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
WiSec 2011 poster: a modular design for a hardware security module in car-to-x communication.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2011

A two-stage verification process for Car-to-X mobility data based on path prediction and probabilistic maneuver recognition.
Proceedings of the 2011 IEEE Vehicular Networking Conference, 2011

State space optimization within the DEVS model of computation for timing efficiency.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis.
Proceedings of the IEEE 10th International Conference on Trust, 2011

A Decentralized Group Privacy Protocol for Vehicular Networks.
Proceedings of the PASSAT/SocialCom 2011, Privacy, 2011

dcTPM: A Generic Architecture for Dynamic Context Management.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A Diffie-Hellman based privacy protocol for Car-to-X communication.
Proceedings of the Ninth Annual Conference on Privacy, Security and Trust, 2011

Enhancing FPGA Robustness via Generic Monitoring IP Cores.
Proceedings of the PECCS 2011, 2011

Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms.
Proceedings of the HOST 2011, 2011

Hardware-accelerated execution of Pi-calculus reconfiguration schedules.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A novel architecture for a secure update of cryptographic engines on trusted platform module.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem.
IEEE Trans. Computers, 2010

A Course on Reconfigurable Processors.
ACM Trans. Comput. Educ., 2010

A Demonstrator for Beamforming in C2X Communication.
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

Enhancing Security and Privacy in C2X Communication by Radiation Pattern Control.
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010

Ray - a secure micro kernel architecture.
Proceedings of the Eighth Annual Conference on Privacy, Security and Trust, 2010

Interactive Optimization of FPGA-based Systems-on-Chips.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Verification of dynamically reconfigurable embedded systems by model transformation rules.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Virtualization within a Parallel Array of Homogeneous Processing Units.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Reconfigurable Computing Education in Computer Science.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
High-Performance Rekeying Processor Architecture for Group Key Management.
IEEE Trans. Computers, 2009

Optimized Implementation of Elliptic Curve Based Additive Homomorphic Encryption for Wireless Sensor Networks
CoRR, 2009

Embedded systems for IT security applications: properties and design considerations.
Proceedings of the 2nd International Conference on Security of Information and Networks, 2009

An efficient reliability evaluation approach for system-level design of embedded systems.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A compact error model for reliable system design.
Proceedings of the 2009 International Conference on High Performance Computing & Simulation, 2009

Understanding physical models in VHDL-AMS.
Proceedings of the Forum on specification and Design Languages, 2009

DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code.
Proceedings of the Forum on specification and Design Languages, 2009

SC-DEVS: An efficient SystemC extension for the DEVS model of computation.
Proceedings of the Design, Automation and Test in Europe, 2009

A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation.
J. Signal Process. Syst., 2008

Schlüsselverwaltung im Sicheren Multicast.
Proceedings of the Sicherheit 2008: Sicherheit, 2008

A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Specification and Design Considerations for Reliable Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Reliable Performance Evaluation of Rekeying Algorithms in Secure Multicast.
Proceedings of the 2007 International Symposium on a World of Wireless, 2007

Secure Multicast Rekeying: A Case Study for HW/SW-Codesign.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation.
Proceedings of the FPL 2007, 2007

Mixed-Level Modeling Using Configurable MOS Transistor Models.
Proceedings of the Forum on specification and Design Languages, 2007

High-Flexibility Rekeying Processor for Key Management in Secure Multicast.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
Resource Management for Dynamic Reconfigurable Hardware Structures.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Konzept zur Taskmigration auf heterogenen rekonfigurierbaren Rechenplattformen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Architecture refinements by code refactoring of behavioral VHDL-AMS models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Analog circuit synthesis: a search for the Holy Grail?
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel memory architecture for elliptic curve cryptography with parallel modular multipliers.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Supporting AMS-System Design.
Proceedings of the Forum on specification and Design Languages, 2006

2005
Efficient algorithms for multilevel power estimation of VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2005

PEAC: Ein partieller Evaluator für eingebettete Software.
Softwaretechnik-Trends, 2005

A Case Study on Partial Evaluation in Embedded Software Design.
Proceedings of the Third IEEE Workshop on Software Technologies for Future Embedded and Ubiquitous Systems, 2005

RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Synchronisierungsprobleme von Schaltwerken in Wave Pipelining Architektur und ihre Auswirkungen auf die Wahl der Schaltungstechnik.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

A Dependability-Driven System-Level Design Approach for Embedded Systems.
Proceedings of the 2005 Design, 2005

2004
FPGA based hardware acceleration for elliptic curve public key cryptosystems.
J. Syst. Softw., 2004

Konzepte zur Beherrschung der Entwurfskomplexität eingebetteter Systeme.
it Inf. Technol., 2004

Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Fast Points-to Analysis for Languages with Structured Types.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Dynamically Reconfigurable Hardware for Object-Oriented Processing.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Audio watermarking algorithm for real-time speech integrity and authentication.
Proceedings of the 6th workshop on Multimedia & Security, 2004

Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems.
Proceedings of the Forum on specification and Design Languages, 2004

2003
A Novel Specification Model for IP-based Design.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2<sup>n</sup>).
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

2001
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

2000
xCDM -- Ein interaktives Werkzeug zur graphenbasierten Systemmodellierung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
High-Level Embedded System Specifications Based on Process Activation Conditions.
J. VLSI Signal Process., 1999

Functional Specification of Distributed Digital Image Processing Systems by Process Interface Descriptions.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Asynchronous wave pipelines for high throughput datapaths.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks.
Proceedings of the 1998 Design, 1998

1996
Praktikum des modernen VLSI-Entwurfs
Vieweg+Teubner Verlag, ISBN: 978-3-519-02296-1, 1996

1995
Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior.
Proceedings of the Proceedings 11th International IEEE Symposium on Visual Languages, 1995

Logic Reduction in Timed Asynchronous Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Scheduling of Signal Transition Graphs under Timing Constraints.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Software/hardware Co-Design in the MuSE environment.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Object-oriented representation, analysis, and scheduling of signal transition graphs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1982
Zur interaktiven Optimierung integrierter Schaltungen.
PhD thesis, 1982


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