Sören Tempel

According to our database, Sören Tempel authored at least 19 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics.

Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler

CoRR, 2024

2023

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

IEEE Internet Things J., June, 2023

Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Dataset, January, 2023

Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture.

Sören Tempel, Tobias Brandt, Christoph Lüth

Proceedings of the Trends in Functional Programming - 24th International Symposium, 2023

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models.

Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler

Proceedings of the Forum on Specification & Design Languages, 2023

2022

Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Dataset, July, 2022

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

J. Syst. Archit., 2022

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

IEEE Embed. Syst. Lett., 2022

3D Visualization of Symbolic Execution Traces.

Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the Forum on Specification & Design Languages, 2022

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the Automated Technology for Verification and Analysis, 2022

Automated Detection of Spatial Memory Safety Violations for Constrained Devices.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Dataset, September, 2021

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.

Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler

J. Syst. Archit., 2021

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the 24th Forum on specification & Design Languages, 2021

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing.

Sören Tempel, Vladimir Herdt, Rolf Drechsler

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Mutation-based Compliance Testing for RISC-V.

Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

RIOT-POLICE: An implementation of spatial memory safety for the RIOT operating system.

Sören Tempel, Tristan Bruns

CoRR, 2020

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.

Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler

Proceedings of the 38th IEEE International Conference on Computer Design, 2020