Sooryeong Lee

According to our database1, Sooryeong Lee authored at least 11 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A New ISA for High-Speed and Area-Efficient ALPG.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

RA-Aware Fail Data Collection Architecture for Cost Reduction.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

A New Fail Address Memory Architecture for Cost-Effective ATE.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

APAPG: Address Pre-Processed ALPG for High-Speed Linear Test.
Proceedings of the 21st International SoC Design Conference, 2024

Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis.
Proceedings of the 21st International SoC Design Conference, 2024

2023
Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022
An Improved Early Termination Methodology Using Convolutional Neural Network.
Proceedings of the 19th International SoC Design Conference, 2022

FAME: Fault Address Memory Structure for Repair Time Reduction.
Proceedings of the 19th International SoC Design Conference, 2022

PROG: Per-Row Output Generator for BOST.
Proceedings of the 19th International SoC Design Conference, 2022

2021
A Circular-based TSV Repair Architecture.
Proceedings of the 18th International SoC Design Conference, 2021

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.
Proceedings of the 18th International SoC Design Conference, 2021


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