Soonyoung Cha

Orcid: 0000-0003-3148-256X

According to our database1, Soonyoung Cha authored at least 10 papers between 2014 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

2015
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectron. Reliab., 2015

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectron. Reliab., 2015

AVERT: An elaborate model for simulating variable retention time in DRAMs.
Microelectron. Reliab., 2015

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab., 2015

Processor-level reliability simulator for time-dependent gate dielectric breakdown.
Microprocess. Microsystems, 2015

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Estimation of remaining life using embedded SRAM for wearout parameter extraction.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

2014
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014


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