Soonyoung Cha
Orcid: 0000-0003-3148-256X
According to our database1,
Soonyoung Cha
authored at least 11 papers
between 2014 and 2018.
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Bibliography
2018
Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system.
PhD thesis, 2018
2017
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017
2015
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown.
Microelectron. Reliab., 2015
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab., 2015
Microprocess. Microsystems, 2015
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015
2014
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014