Soonsung Ahn

According to our database, Soonsung Ahn authored at least 5 papers between 2020 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique.

Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim

IEEE J. Solid State Circuits, 2022

An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter.

Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, Chulwoo Kim

IEEE J. Solid State Circuits, 2022

2021

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs.

Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soonsung Ahn, Sooho Park, Chulwoo Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier.

Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, Chulwoo Kim

IEEE J. Solid State Circuits, 2020

A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique.

Soonsung Ahn, Jaegeun Song, Chaegang Lim, Yohan Choi, Sooho Park, Yunsoo Park, Chulwoo Kim

Proceedings of the International SoC Design Conference, 2020