Soon-Jyh Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A Physically Unclonable Function Embedded in a SAR ADC.

[BibT_eX]

[DOI]

Yi-Ying Chen

Proceedings of the IEEE International Test Conference in Asia, 2022

A 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Jun-Hui Fu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration.

[BibT_eX]

[DOI]

Che-Wei Hsu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Detection System for Capacitive Plantar Pressure Monitoring.

[BibT_eX]

[DOI]

Tzung-Min Tsai

Shuenn-Yuh Lee

IEEE Access, 2020

A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator.

[BibT_eX]

[DOI]

Yu-Sian Lin

Chia-Ling Wei

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Resistor-Based Temperature Sensing Chip with Digital Output.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Modified BER Test for SAR ADCs.

[BibT_eX]

[DOI]

Chia-Chuan Li

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC.

[BibT_eX]

[DOI]

Huan-Jui Hu

Yi-Shen Cheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration.

[BibT_eX]

[DOI]

Yi-Shen Cheng

Huan-Jui Hu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A 12-b 40-MS/s Calibration-Free SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

A quick jitter tolerance estimation technique for bang-bang CDRs.

[BibT_eX]

[DOI]

Yen-Long Lee

Proceedings of the International Test Conference in Asia, 2017

A low power duobinary voltage mode transmitter.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

A 12-bit 40-MS/s calibration-free SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A Systematic Design Methodology of Asynchronous SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.

[BibT_eX]

[DOI]

Chun-Po Huang

IEEE Trans. Instrum. Meas., 2016

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A pipeline ADC with latched-based ring amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2015

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits.

[BibT_eX]

[DOI]

Jih Ren Goh

Yen-Long Lee

Proceedings of the VLSI Design, Automation and Test, 2015

A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2014

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2014

Low power pipelined SAR ADC with loading-free architecture.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

An area- and power-efficient half-rate clock and data recovery circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Heart rate detection through bone-conduction headset.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

A 10b 100kS/s SAR ADC with charge recycling switching method.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A successive approximation ADC with resistor-capacitor hybrid structure.

[BibT_eX]

[DOI]

Ting-Zi Chen

Guan-Ying Huang

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications.

[BibT_eX]

[DOI]

Ren-Li Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers.

[BibT_eX]

[DOI]

Ren-Li Chen

IET Circuits Devices Syst., 2012

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A 1-V, 44.6 ppm/°C bandgap reference with CDS technique.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Routability-driven placement algorithm for analog integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

A power-efficient sizing methodology of SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A 1-V CDS bandgap reference without on-chip resistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

A Design of Linearity Built-in Self-Test for Current-Steering DAC.

[BibT_eX]

[DOI]

Su-Ling Huang

J. Electron. Test., 2011

A SAR ADC BIST for simplified linearity test.

[BibT_eX]

[DOI]

An-Sheng Chao

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme.

[BibT_eX]

[DOI]

Cheng-Wu Lin

IEEE Trans. Very Large Scale Integr. Syst., 2010

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Performance-driven analog placement considering boundary constraint.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique.

[BibT_eX]

[DOI]

Chih-Hao Huang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Jitter Characterizing BIST with Pulse-Amplifying Technique.

[BibT_eX]

[DOI]

An-Sheng Chao

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Histogram-Based Testing Method for Estimating A/D Converter Performance.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2008

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2008

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture.

[BibT_eX]

[DOI]

Hsin-Hung Ou

IEICE Trans. Electron., 2008

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture.

[BibT_eX]

[DOI]

Hsin-Hung Ou

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Reduced Code Linearity Test Method for Pipelined A/D Converters.

[BibT_eX]

[DOI]

Te-Chieh Kung

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.

[BibT_eX]

[DOI]

Lih-Yih Chiou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Histogram Based Testing Strategy for ADC.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.

[BibT_eX]

[DOI]

Chih-Haur Huang

Kuen-Jong Lee

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits.

[BibT_eX]

[DOI]

Chung-Len Lee

Jwu E. Chen

J. Inf. Sci. Eng., 2003

A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.

[BibT_eX]

[DOI]

Kuen-Jong Lee

Ruei-Shiuan Tzeng

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Structural Fault Based Specification Reduction for Testing Analog Circuits.

[BibT_eX]

[DOI]

Chung-Len Lee

Jwu E. Chen

J. Electron. Test., 2002

1999

A DFT for semi-DC fault diagnosis for switched-capacitor circuits.

[BibT_eX]

[DOI]

Proceedings of the 4th European Test Workshop, 1999

1997

Functional test pattern generation for CMOS operational amplifier.

[BibT_eX]

[DOI]