Soo-Ik Chae

IEEE Trans. Circuits Syst. Video Technol., 2021

2019

An adaptive hash-based search for integer motion estimation in SCC.

[BibT_eX]

[DOI]

Youngkyu Choi

Hyuk-Jae Lee

IEICE Electron. Express, 2019

2018

Fast Integer Motion Estimation With Bottom-Up Motion Vector Prediction for an HEVC Encoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2018

2016

Decoding of main 4: 2: 2 10-bit bitstreams in HEVC Main 8-bit best-effort decoders.

[BibT_eX]

[DOI]

Woo Seok Jeong

Hyunmin Jung

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

2015

Coding efficiency of AVS 2.0 for CBAC and CABAC engines.

[BibT_eX]

[DOI]

Jing Cui

Youngkyu Choi

Proceedings of the Eighth International Conference on Machine Vision, 2015

Coding efficiency of the context-based arithmetic coding engine of AVS 2.0 in the HEVC encoder.

[BibT_eX]

[DOI]

Hyunmin Jung

Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2013

Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders.

[BibT_eX]

[DOI]

Jicheon Kim

IEEE Trans. Consumer Electron., 2013

Next-Generation Memory [Guest editors' introduction].

[BibT_eX]

[DOI]

Greg Atwood

Simon S. Y. Shim

Computer, 2013

Generation of efficient bitstreams for functional tests of video decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2011

A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2011

2010

Constrained-random bitstream generation for H.264/AVC decoder conformance test.

[BibT_eX]

[DOI]

Jinhyun Cho

IEEE Trans. Consumer Electron., 2010

Flexible DMA subsystem in multi-core platforms for video applications.

[BibT_eX]

[DOI]

Moonmo Koo

IEICE Electron. Express, 2010

A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

A mixed-level virtual prototyping environment for SystemC-based design methodology.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Simulink<sup>®</sup>-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.

[BibT_eX]

[DOI]

Integr., 2009

Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator.

[BibT_eX]

[DOI]

Daewoong Kim

Kilhyung Cha

IEICE Trans. Inf. Syst., 2009

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008

A high-performance OpenVG accelerator with dual-scanline filling rendering.

[BibT_eX]

[DOI]

Daewoong Kim

Kilhyung Cha

IEEE Trans. Consumer Electron., 2008

Cache Optimization for H.264/AVC Motion Compensation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

A hardware operating system kernel for multi-processor systems.

[BibT_eX]

[DOI]

Do-sun Hong

IEICE Electron. Express, 2008

RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow.

[BibT_eX]

[DOI]

Jinhyun Cho

Proceedings of the Forum on specification and Design Languages, 2008

2007

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2007

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.

[BibT_eX]

[DOI]

Kai Huang

Katalin Popovici

Proceedings of the 44th Design Automation Conference, 2007

2006

A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2006

A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Buffer memory optimization for video codec application modeled in Simulink.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Reusable component IP design using refinement-based design environment.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Functional modeling techniques for efficient SW code generation of video codec applications.

[BibT_eX]

[DOI]

Ahmed Amine Jerraya

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring.

[BibT_eX]

[DOI]

Ren Huang

Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005

A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A C/C++-Based Functional Verification Framework Using the SystemC Verification Library.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A Two-Week Program for a Platform-Based SoC Design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Complexity reduction in an nRERL microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.

[BibT_eX]

[DOI]

Proceedings of the Second Conference on Computing Frontiers, 2005

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264.

[BibT_eX]

[DOI]

Minho Kim

Ingu Hwang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A reset-free anti-harmonic delay-locked loop using a cycle period detector.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2003

A cycle-accurate joulemeter for CMOS VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

2001

Partial bus-invert coding for power optimization of application-specific systems.

[BibT_eX]

[DOI]

Youngsoo Shin

Kiyoung Choi

IEEE Trans. Very Large Scale Integr. Syst., 2001

An 8-b nRERL microprocessor for ultra-low-energy applications.

[BibT_eX]

[DOI]

Jun-Ho Kwon

Proceedings of ASP-DAC 2001, 2001

2000

nMOS reversible energy recovery logic for ultra-low-energy applications.

[BibT_eX]

[DOI]

Dong-Gyu Kim

IEEE J. Solid State Circuits, 2000

Emulator Environment Based on an FPGA Prototyping Board.

[BibT_eX]

[DOI]

Kyung-soo Oh

Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).

[BibT_eX]

[DOI]

Koichi Nose

Takayasu Sakurai

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A three-port nRERL register file for ultra-low-energy applications.

[BibT_eX]

[DOI]

Jun-Ho Kwon

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Frequency-domain separation of convolved non-stationary signals with adaptive non-causal FIR filters.

[BibT_eX]

[DOI]

Kyungmin Na

Kyung Jin Lee

Proceedings of the 10th European Signal Processing Conference, 2000

An 8×8 nRERL serial multiplier for ultra-low-power aplications.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems.

[BibT_eX]

[DOI]

Dong-Gyu Kim

IEEE J. Solid State Circuits, 1999

1998

New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding.

[BibT_eX]

[DOI]

Seongsoo Lee

Jeong-Min Kim

IEEE Trans. Circuits Syst. Video Technol., 1998

Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 1998

Partial bus-invert coding for power optimization of system level bus.

[BibT_eX]

[DOI]

Youngsoo Shin

Kiyoung Choi

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997

Digital implementation of discrete-time cellular neural networks with distributed arithmetic.

[BibT_eX]

[DOI]

Sungjun Park

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

Improved sufficient convergence condition for the discrete-time cellular neural networks.

[BibT_eX]

[DOI]

Sungjun Park

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

Single-sensor active noise cancellation using recurrent neural network predictors.

[BibT_eX]

[DOI]

Kyungmin Na

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1996

Two-step motion estimation algorithm using low-resolution quantization.

[BibT_eX]

[DOI]

Seongsoo Lee

Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

Fast vector quantizer using multiple sorted index tables.

[BibT_eX]

[DOI]

Sun-Young Choi

Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

GPD training of the state weighting functions in hidden control neural network.

[BibT_eX]

[DOI]

Kyungmin Na

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995

New Perceptron Model Using Random Bitstreams.

[BibT_eX]

[DOI]

Neural Comput., 1995

Recurrent neural prediction models for speech recognition.

[BibT_eX]

[DOI]

Proceedings of the Fourth European Conference on Speech Communication and Technology, 1995

Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method.

[BibT_eX]

[DOI]

Proceedings of the Fourth European Conference on Speech Communication and Technology, 1995

Corrective training of hidden control neural network.

[BibT_eX]

[DOI]

KyungMin Na

SouGuil Ann

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Ratio pulse arithmetic for radial basis function network.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

New classifier with reduced computational complexity.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994

Stereo Correspondence with Discrete-Time Cellular Neural Networks.

[BibT_eX]

[DOI]

Sungjun Park

Seung-Jai Min

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses.

[BibT_eX]

[DOI]

Seung-Jai Min

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm.

[BibT_eX]

Jae-Hee Won