Songming Yu
Orcid: 0000-0002-6191-2682
According to our database1,
Songming Yu
authored at least 7 papers
between 2020 and 2024.
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Bibliography
2024
A Heterogeneous Microprocessor for Intermittent AI Inference Using Nonvolatile-SRAM-Based Compute-In-Memory.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
2023
A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
2020
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020