Song Chen

According to our database, Song Chen authored at least 147 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits.

Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration.

Haitao Du, Yuhan Qin, Song Chen, Yi Kang

ACM Trans. Archit. Code Optim., June, 2024

Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay.

Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, Yi Kang

ACM Trans. Design Autom. Electr. Syst., May, 2024

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM.

Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

AD²VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems.

Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang

ACM Trans. Design Autom. Electr. Syst., January, 2024

Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.

Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang

IEEE Trans. Computers, January, 2024

Load Balanced PIM-Based Graph Processing.

Xiang Zhao, Song Chen, Yi Kang

ACM Trans. Design Autom. Electr. Syst., 2024

Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems.

Mengke Ge, Junpeng Wang, Binhan Chen, Yingjian Zhong, Haitao Du, Song Chen, Yi Kang

CoRR, 2024

Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration.

Wendi Sun, Wenhao Sun, Yifan Wang, Yi Kang, Song Chen

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner.

Bo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ILP-based Multi-Branch CNNs Mapping on Processing-in-Memory Architecture.

Haodong Han, Junpeng Wang, Bo Ding, Song Chen

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources.

Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang

ACM Trans. Design Autom. Electr. Syst., November, 2023

BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array.

Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, Yi Kang

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.

Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays.

Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen, Yi Kang

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.

Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang

ACM Trans. Design Autom. Electr. Syst., January, 2023

DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems.

Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang

ACM Trans. Design Autom. Electr. Syst., 2023

Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems.

Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu

IEEE Trans Autom. Sci. Eng., 2023

IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product.

Wenhao Sun, Wendi Sun, Song Chen, Yi Kang

CoRR, 2023

AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect.

Zihao Xuan, Song Chen, Yi Kang

CoRR, 2023

BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array.

Xiaobing Ni, Jiaheng Ruan, Mengke Ge, Wendi Sun, Song Chen, Yi Kang

CoRR, 2023

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM.

Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang

CoRR, 2023

Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity.

Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang

CoRR, 2023

Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch.

Shahzad Haider, Ke Hu, Song Chen

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems.

Shahzad Haider, Junhao Liang, Song Chen

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches.

Shahzad Haider, Song Chen

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution.

Zetao Guo, Junpeng Wang, Song Chen, Yi Kang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Restructure-Tolerant Timing Prediction via Multimodal Fusion.

Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm.

Bin Zhang, Haitao Du, Song Chen, Yi Kang

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.

Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips.

Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu

ACM Trans. Design Autom. Electr. Syst., 2022

A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching.

Zhimin Lu, Jue Wang, Zhiwei Li, Song Chen, Feng Wu

IEEE Trans. Circuits Syst. Video Technol., 2022

Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs.

Mengke Ge, Xiaobing Ni, Song Chen, Yi Kang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC.

Qi Xu, Wenhao Sun, Song Chen, Yi Kang, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.

Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning.

Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Real-time infrared small target detection network and accelerator design.

Ke Hu, Wenhao Sun, Zhongbo Nie, Ran Cheng, Song Chen, Yi Kang

Integr., 2022

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs.

Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang

CoRR, 2022

Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks.

Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Junpeng Wang, Yi Kang, Song Chen

CoRR, 2022

Multi-scale Lightweight Neural Network for Real-Time Object Detection.

Yuan Li, Qiaojun Wu, Song Chen, Yi Kang

Proceedings of the PRICAI 2022: Trends in Artificial Intelligence, 2022

PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering.

Bin Zhang, Haitao Du, Song Chen, Yi Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer.

Yifan Song, Shunpeng Zhao, Song Chen, Yi Kang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

Real-time CNN-based keypoint detector with Sobel filter and descriptor trained with keypoint candidates.

Ke Hu, Xun Yuan, Song Chen

Proceedings of the Fifteenth International Conference on Machine Vision, 2022

DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection.

Qiaojun Wu, Yuan Li, Song Chen, Yi Kang

Proceedings of the Data Mining and Big Data - 7th International Conference, 2022

2021

A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier.

Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang

Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021

A Low-latency NoC Router Priority Scheme for BFS algorithm.

Lei Ding, Haitao Du, Song Chen, Yi Kang

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Reliability-Driven Neuromorphic Computing Systems Design.

Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Effects of using Multi Voltage Threshold Transistors in Asynchronous Circuits.

Shahzad Haider, Song Chen

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Low Power Branch Prediction for Deep Learning on RISC-V Processor.

Mingjian Sun, Yuan Li, Song Chen, Yi Kang

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.

Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu

ACM Trans. Design Autom. Electr. Syst., 2020

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.

Song Chen, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips.

Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, Feng Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Fault tolerance in memristive crossbar-based neuromorphic computing systems.

Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang

Integr., 2020

Realtime CNN-based Keypoint Detector with Sobel Filter and CNN-based Descriptor Trained with Keypoint Candidates.

Xun Yuan, Ke Hu, Song Chen

CoRR, 2020

Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.

Junpeng Wang, Qi Xu, Bo Yuan, Song Chen, Bei Yu, Feng Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

SaD-SLAM: A Visual SLAM Based on Semantic and Depth Information.

Xun Yuan, Song Chen

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems.

Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems.

Yuting Wu, Bo Ding, Qi Xu, Song Chen

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

Adaptive 3D-IC TSV Fault Tolerance Structure Generation.

Song Chen, Qi Xu, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis.

Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu

Integr., 2019

High throughput hardware architecture for accurate semi-global matching.

Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, Song Chen

Integr., 2019

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems.

Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen

Integr., 2019

Low-Resource Hardware Architecture for Semi-Global Stereo Matching.

Jue Wang, Zhiwei Li, Lan Yao, Song Chen, Feng Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN.

Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen, Yi Kang, Feng Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network.

Baicheng Liu, Song Chen, Yi Kang, Feng Wu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Power-gating-aware scheduling with effective hardware resources optimization.

Nan Wang, Wei Zhong, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu

Integr., 2018

Lagrangian relaxation-based routing path allocation for application-specific network-on-chips.

Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen

Integr., 2018

Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems.

Song Chen, Jinglei Huang, Xiaodong Xu, Qi Xu

CoRR, 2018

Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis.

Nan Wang, Song Chen, Jianmo Ni, Xiaofeng Ling, Yu Zhu

IEEE Access, 2018

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints.

Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.

Qi Xu, Song Chen, Bei Yu, Feng Wu

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits.

Qi Xu, Song Chen, Xiaodong Xu, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Fast thermal analysis for fixed-outline 3D floorplanning.

Qi Xu, Song Chen

Integr., 2017

AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products.

Gan Feng, Lan Yao, Song Chen

Integr., 2017

Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs.

Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen

Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs.

Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Memristor-based material implication logic design for full adders.

Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen, Feng Wu

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth.

Zhiwei Li, Yan Li, Song Chen, Feng Wu

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Integer linear programming based fault-tolerant topology synthesis for application-specific NoC.

Zhigang Li, Jinglei Huang, Qi Xu, Song Chen

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.

Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2016

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect.

Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin

ACM Trans. Design Autom. Electr. Syst., 2016

Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning.

Qi Xu, Song Chen, Bin Li

Appl. Soft Comput., 2016

Real-Time Hardware Stereo Matching Using Guided Image Filter.

Chen Yang, Yan Li, Wei Zhong, Song Chen

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Irregularly shaped voltage islands generation with hazard and heal strategy.

Zhen Meng, Song Chen, Lu Huang

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi.

Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips.

Jinglei Huang, Zhigang Li, Wei Zhong, Song Chen

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis.

Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Leakage Power Aware Scheduling in High-Level Synthesis.

Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips.

Wei Zhong, Song Chen, Bo Huang, Takeshi Yoshimura, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs.

Nan Liu, Song Chen, Takeshi Yoshimura

IEICE Trans. Electron., 2013

Min-cut based leakage power aware scheduling in high-level synthesis.

Nan Wang, Song Chen, Takeshi Yoshimura

Proceedings of the International Symposium on Quality Electronic Design, 2013

Delay-driven layer assignment in global routing under multi-tier interconnect structure.

Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto

Proceedings of the International Symposium on Physical Design, 2013

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis.

Nan Wang, Song Chen, Yuhuan Sun, Takeshi Yoshimura

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis.

Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis.

Cong Hao, Song Chen, Takeshi Yoshimura

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs.

Wei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Power and resource aware scheduling with multiple voltages.

Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Interconnection allocation between functional units and registers in High-Level Synthesis.

Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.

Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto

IEICE Trans. Electron., 2012

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.

Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Floorplanning for High Utilization of Heterogeneous FPGAs.

Nan Liu, Song Chen, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Port assignment for interconnect reduction in high-level synthesis.

Cong Hao, Song Chen, Takeshi Yoshimura

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Application-Specific Network-on-Chip synthesis with topology-aware floorplanning.

Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Practically scalable floorplanning with voltage island generation.

Song Chen, Xiaolin Zhang, Takeshi Yoshimura

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Linear optimal one-sided single-detour algorithm for untangling twisted bus.

Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.

Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Novel and efficient min cut based voltage assignment in gate level.

Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Floorplanning driven Network-on-Chip synthesis for 3-D SoCs.

Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, Satoshi Goto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.

Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

An effecient level-shifter floorplanning method for Multi-voltage design.

Xiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Mobility overlap-removal based timing-constrained scheduling.

Song Chen, Yuan Yao, Takeshi Yoshimura

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Through-Silicon-Via assignment for 3D ICs.

Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.

Song Chen, Takeshi Yoshimura

Integr., 2010

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density.

Song Chen, Jianwei Shen, Wei Guo, Mei-Fang Chiang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Whitespace insertion for through-silicon via planning on 3-D SoCs.

Wei Zhong, Song Chen, Takeshi Yoshimura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A revisit to voltage partitioning problem.

Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Floorplanning and topology generation for application-specific network-on-chip.

Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Post-scheduling frequency assignment for energy-efficient high-level synthesis.

Ru Liu, Song Chen, Takeshi Yoshimura

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Exploration of Schedule Space by Random Walk.

Liangwei Ge, Song Chen, Takeshi Yoshimura

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Voltage and Level-Shifter Assignment Driven Floorplanning.

Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs.

Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A generalized V-shaped multilevel method for large scale floorplanning.

Song Chen, Zheng Xu, Takeshi Yoshimura

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Voltage-island driven floorplanning considering level-shifter positions.

Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.

Song Chen, Takeshi Yoshimura

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.

Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura

IPSJ Trans. Syst. LSI Des. Methodol., 2008

2007

Max-Flow Scheduling in High-Level Synthesis.

Liangwei Ge, Song Chen, Kazutoshi Wakabayashi, Takashi Takenaka, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A stable fixed-outline floorplanning method.

Song Chen, Takeshi Yoshimura

Proceedings of the 2007 International Symposium on Physical Design, 2007

2006

VLSI Block Placement With Alignment Constraints.

Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Buffer planning based on block exchanging.

Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence.

Song Chen, Takeshi Yoshimura

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Performance constrained floorplanning based on partial clustering [IC layout].

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A New Buffer Planning Algorithm Based on Room Resizing.

Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen

Proceedings of the Embedded and Ubiquitous Computing, 2005

2004

Fast Evaluation of Bounded Slice-Line Grid.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu

J. Comput. Sci. Technol., 2004

A buffer planning algorithm for chip-level floorplanning.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu

Sci. China Ser. F Inf. Sci., 2004

Buffer allocation algorithm with consideration of routing congestion.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing.

Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

An integrated floorplanning with an efficient buffer planning algorithm.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 40th Design Automation Conference, 2003

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing.

Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.

Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003