Song Bian

Orcid: 0000-0003-0467-6203

Affiliations:
  • Beihang University, Beijing, China
  • Kyoto University, Department of Communications and Computer Engineering, Japan (PhD 2019)


According to our database1, Song Bian authored at least 53 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

ArcEDB: An Arbitrary-Precision Encrypted Database via (Amortized) Modular Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2024

APACHE: A Processing-Near-Memory Architecture for Multi-Scheme Fully Homomorphic Encryption.
CoRR, 2024

Oblivious Monitoring for Discrete-Time STL via Fully Homomorphic Encryption.
Proceedings of the Runtime Verification - 24th International Conference, 2024

ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

HOGE: Homomorphic Gate on An FPGA.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Adaptive hyperparameter optimization for black-box adversarial attack.
Int. J. Inf. Sec., December, 2023

HEIR: A Unified Representation for Cross-Scheme Compilation of Fully Homomorphic Computation.
IACR Cryptol. ePrint Arch., 2023

HE<sup>3</sup>DB: An Efficient and Elastic Encrypted Database Via Arithmetic-And-Logic Fully Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2023

On Hyperdimensional Computing-based Federated Learning: A Case Study.
Proceedings of the International Joint Conference on Neural Networks, 2023

THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PIMA-LPN: Processing-in-memory Acceleration for Efficient LPN-based Post-Quantum Cryptography.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

HE3DB: An Efficient and Elastic Encrypted Database Via Arithmetic-And-Logic Fully Homomorphic Encryption.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

2022
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks.
IEEE Trans. Computers, 2022

HEDA: Multi-Attribute Unbounded Aggregation over Homomorphically Encrypted Database.
Proc. VLDB Endow., 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.
IEEE Internet Things J., 2022

Oblivious Online Monitoring for Safety LTL Specification via Fully Homomorphic Encryption.
Proceedings of the Computer Aided Verification - 34th International Conference, 2022

Approximate Computing for Cryptography.
Proceedings of the Approximate Computing, 2022

2021
APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations.
IEEE Trans. Inf. Forensics Secur., 2021

Clonable PUF: On the Design of PUFs That Share Equivalent Responses.
IACR Cryptol. ePrint Arch., 2021

Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs.
IACR Cryptol. ePrint Arch., 2021

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE.
Proceedings of the 30th USENIX Security Symposium, 2021

Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE.
Proceedings of the WAHC '21: Proceedings of the 9th on Workshop on Encrypted Computing & Applied Homomorphic Cryptography, 2021

2020
FedNNNN: Norm-Normalized Neural Network Aggregation for Fast and Accurate Federated Learning.
CoRR, 2020

AutoPrivacy: Automated Layer-wise Parameter Selection for Secure Neural Network Inference.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

BUNET: Blind Medical Image Segmentation Based on Secure UNET.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

NASS: Optimizing Secure Inference via Neural Architecture Search.
Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020

Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Realizing Homomorphic Secure Protocols through Cross-Layer Design Techniques.
PhD thesis, 2019

Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A study on NBTI-induced delay degradation considering stress frequency dependence.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

DWE: decrypting learning with errors with errors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Identification and Application of Invariant Critical Paths under NBTI Degradation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

SCAM: Secured content addressable memory based on homomorphic encryption.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.
Proceedings of the 25th IEEE Asian Test Symposium, 2016


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