Soner Yaldiz

According to our database, Soner Yaldiz authored at least 25 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

2023

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.

Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., September, 2023

Analog Layout Automation On Advanced Process Technologies.

Soner Yaldiz

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.

Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

ALIGN: A System for Automating Analog Layout.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

IEEE Des. Test, 2021

Machine Learning Techniques in Analog Layout Automation.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.

Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2015

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology.

Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.

Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".

Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, June, 2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.

Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.

Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman

IEEE J. Solid State Circuits, 2013

Formal verification of phase-locked loops using reachability analysis and continuization.

Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry T. Pileggi

Commun. ACM, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.

Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman

Proceedings of the Symposium on VLSI Circuits, 2012

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Indirect phase noise sensing for self-healing voltage controlled oscillators.

Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009

Efficient statistical analysis of read timing failures in SRAM circuits.

Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

SRAM parametric failure analysis.

Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi

Proceedings of the 46th Design Automation Conference, 2009

2008

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study.

Soner Yaldiz, Alper Demir, Serdar Tasiran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2005

Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.

Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005