Somnath Paul
Orcid: 0000-0001-9908-669X
According to our database1,
Somnath Paul
authored at least 67 papers
between 1998 and 2023.
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Bibliography
2023
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
2020
On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them.
Discret. Math. Algorithms Appl., 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019
2018
On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs.
Discret. Math. Algorithms Appl., 2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.
ACM J. Emerg. Technol. Comput. Syst., 2017
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning.
CoRR, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications.
IEEE Trans. Computers, 2016
Discret. Math. Algorithms Appl., 2016
CoRR, 2016
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
2014
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Discret. Math. Algorithms Appl., 2014
Discret. Math. Algorithms Appl., 2014
Robust low-power reconfigurable computing with a variation-aware preferential design approach.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Computers, 2013
Discret. Math. Algorithms Appl., 2013
An Improved <i>g</i> <sub> <i>m</i> </sub>/<i>I</i> <sub> <i>D</i> </sub> Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Discret. Math. Algorithms Appl., 2012
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.
Proceedings of the 25th International Conference on VLSI Design, 2012
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.
Proceedings of the 25th International Conference on VLSI Design, 2012
2011
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.
IEEE Trans. Computers, 2011
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
2010
Low-overhead <i>F</i><sub><i>max</i></sub> calibration at multiple operating points using delay-sensitivity-based path selection.
ACM Trans. Design Autom. Electr. Syst., 2010
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010
System level self-healing for parametric yield and reliability improvement under power bound.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.
IET Comput. Digit. Tech., 2009
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.
Proceedings of the Design, Automation and Test in Europe, 2008
Reconfigurable computing using content addressable memory for improved performance and resource usage.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Memory based computation using embedded cache for processor yield and reliability improvement.
Proceedings of the 25th International Conference on Computer Design, 2007
Low-overhead design technique for calibration of maximum frequency at multiple operating points.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998