Somnath Banerjee

According to our database, Somnath Banerjee authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Optimized Simulation Acceleration with Partial Testbench Evaluation.

Somnath Banerjee, Tushar Gupta

Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

2012

Efficient Online RTL Debugging Methodology for Logic Emulation Systems.

Somnath Banerjee, Tushar Gupta

Proceedings of the 25th International Conference on VLSI Design, 2012

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation.

Somnath Banerjee, Tushar Gupta

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

A scalable hybrid verification system based on HDL slicing.

Somnath Banerjee, Tushar Gupta, Saurabh Jain

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011