Somayeh Timarchi
Orcid: 0000-0002-7760-3411
According to our database1,
Somayeh Timarchi
authored at least 30 papers
between 2005 and 2025.
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Bibliography
2025
Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications.
J. Supercomput., January, 2025
Load balanced sub-tree decomposition algorithm for solving Mixed Integer Linear Programming models in behavioral synthesis.
Comput. Electr. Eng., 2025
2023
Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
IEEE Access, 2023
2022
Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization.
Microprocess. Microsystems, September, 2022
Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Circuits Syst. Signal Process., 2022
2021
Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix.
Microelectron. J., 2019
Optimized Parity-Based Error Detection and Correction Methods for Residue Number System.
J. Circuits Syst. Comput., 2019
Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2<sup><i>n</i></sup> - 1 Adder and Multiplier.
Circuits Syst. Signal Process., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
Signal Process. Image Commun., 2017
2016
Int. J. Comput. Aided Eng. Technol., 2016
Circuits Syst. Signal Process., 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
2014
Proceedings of the 37th International Convention on Information and Communication Technology, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
2012
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}.
IET Comput. Digit. Tech., 2012
2010
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2<sup>n</sup> -1, 2<sup>n</sup>, 2<sup>n</sup> +1, 2<sup>2n + 1</sup>-1 and 2<sup>n</sup> -1, 2<sup>n</sup> +1, 2<sup>2n</sup>, 2<sup>2n</sup> +1 Based on New CRTs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A unified addition structure for moduli set {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation.
Proceedings of the 28th International Conference on Computer Design, 2010
2009
IEICE Electron. Express, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2005
Evaluation of Some Exponential Random Number Generators Implemented by FPGA.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005