Somashekara Bhat

According to our database, Somashekara Bhat authored at least 6 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure.

Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat

J. Circuits Syst. Comput., 2022

2020

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review.

Vinod Kumar Joshi, Prashanth Barla, Somashekara Bhat, Brajesh Kumar Kaushik

IEEE Access, 2020

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit.

Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat

IEEE Access, 2020

2019

Accelerometer based quantitative outcome measurement for hand function test.

K. Aneesha Acharya, Somashekara Bhat, M. Kanthi

Int. J. Sens. Networks, 2019

Load Cell and FSR-Based Hand-Assistive Device.

K. Aneesha Acharya, Somashekara Bhat, M. Kanthi

Proceedings of the Progress in Advanced Computing and Intelligent Engineering, 2019

2011

Modified reduced delay BCD adder.

C. Sundaresan, C. V. S. Chaitanya, P. R. Venkateswaran, Somashekara Bhat, J. Mohan Kumar

Proceedings of the 4th International Conference on Biomedical Engineering and Informatics, 2011