Soichiro Hosoda

According to our database, Soichiro Hosoda authored at least 4 papers between 2012 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2020

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.

Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda

IEEE J. Solid State Circuits, 2020

2019

A 20.5TOPS and 217.3GOPS/mm² Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.

Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2014

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.

Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe

IEICE Trans. Electron., 2014

2012

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.

Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori

Proceedings of the Symposium on VLSI Circuits, 2012