Sohan Purohit
According to our database1,
Sohan Purohit
authored at least 21 papers
between 2008 and 2014.
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Bibliography
2014
Circuits Syst. Signal Process., 2014
2013
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
2012
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011
2010
J. Low Power Electron., 2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Design of self correcting radiation hardened digital circuits using decoupled ground bus.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008