Sohaib Majzoub
Orcid: 0000-0003-3196-2635
According to our database1,
Sohaib Majzoub
authored at least 32 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Proceedings of the 2024 8th International Conference on Cloud and Big Data Computing, 2024
2023
Circuits Syst. Signal Process., November, 2023
Fast Electrochemical Impedance Measurement and Classification System Based on Machine Learning Algorithms.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Using Electrical Impedance Tomography and Machine Learning for Breast Cancer Detection.
Proceedings of the 16th International Conference on Developments in eSystems Engineering, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
Hardware Acceleration of the STRIKE String Kernel Algorithm for Estimating Protein to Protein Interactions.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning.
IEEE Access, 2022
Time-Frequency Design of a Multi-Sine Excitation With Random Phase and Controllable Amplitude for (Bio) Impedance Measurements.
IEEE Access, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
A systematic literature review on hardware implementation of artificial intelligence algorithms.
J. Supercomput., 2021
2020
2019
System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.
J. Low Power Electron., 2019
Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators.
Circuits Syst. Signal Process., 2019
IEEE Access, 2019
2015
Reducing random-dopant fluctuation impact using footer transistors in many-core systems.
Integr., 2015
2013
Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms.
Proceedings of the 8th International Design and Test Symposium, 2013
2012
J. Supercomput., 2012
2011
J. Low Power Electron., 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
2010
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 5th International Design and Test Workshop, 2010
2009
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2007
J. Circuits Syst. Comput., 2007
Mapping and Performance Analysis of Lookup Table Implementations on Reconfigurable Platform.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007
2002
Proceedings of the Field-Programmable Logic and Applications, 2002