Sneh Saurabh
Orcid: 0000-0002-0587-3391
According to our database1,
Sneh Saurabh
authored at least 23 papers
between 2018 and 2024.
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Bibliography
2024
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
CoRR, 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis.
IEEE Access, 2021
Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study.
IEEE Access, 2021
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
2020
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis.
IEEE Access, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
2018
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018