Smrutilekha Samanta

Orcid: 0000-0001-9631-372X

According to our database1, Smrutilekha Samanta authored at least 5 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2024
Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique.
Int. J. Circuit Theory Appl., May, 2024

2022
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2020
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2017
Threshold voltage extraction techniques adaptable from sub-micron CMOS to large-area oxide TFT technologies.
Int. J. Circuit Theory Appl., 2017


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