Slawomir Chmielewski

According to our database, Slawomir Chmielewski authored at least 12 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2022

Improving Characteristics of FSMs With Mixed Codes of Outputs.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek

IEEE Access, 2022

2020

Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski

Lecture Notes in Electrical Engineering 636, Springer, ISBN: 978-3-030-38294-0, 2020

Improving Characteristics of LUT-Based Moore FSMs.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

IEEE Access, 2020

2019

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

J. Circuits Syst. Comput., 2019

2018

Design of CPLD-based mealy FSMs with counters.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Design of FPGA-based Mealy FSMs with Counters.

Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski

Proceedings of the 25th International Conference "Mixed Design of Integrated Circuits and System", 2018

2014

Hardware Reduction in CPLD-Based Moore FSM.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

J. Circuits Syst. Comput., 2014

2013

Synthesis of Moore Finite State Machines Based on Pseudoequivalent States.

Alexander Barkalov, Slawomir Chmielewski, Larysa Titarenko

Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

2011

Synthesis of control unit with refined state encoding for CPLD devices.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

Proceedings of the 9th East-West Design & Test Symposium, 2011

2010

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Hardware reduction for FSM - Based control units using PAL technology.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2007

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM.

Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski

Int. J. Appl. Math. Comput. Sci., 2007