Skyler Windh

Orcid: 0000-0002-7489-6300

According to our database1, Skyler Windh authored at least 9 papers between 2015 and 2022.

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Bibliography

2022
Reinforcement Learning Approach for Mapping Applications to Dataflow-Based Coarse-Grained Reconfigurable Array.
CoRR, 2022

2021
Efficient local locking for massively multithreaded in-memory hash-based operators.
VLDB J., 2021

2019
Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads.
ACM Trans. Archit. Code Optim., 2019

2018
Hashing, Caching, and Synchronization: Memory Techniques for Latency Masking Multithreaded Applications.
PhD thesis, 2018

2017
Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
FPGA-accelerated group-by aggregation using synchronizing caches.
Proceedings of the 12th International Workshop on Data Management on New Hardware, 2016

2015
High-Level Language Tools for Reconfigurable Computing.
Proc. IEEE, 2015

An open-source compiler and PCB synthesis tool for digital microfluidic biochips.
Integr., 2015

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015


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