Sjigekazu Yamada

According to our database, Sjigekazu Yamada authored at least 2 papers between 2009 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories.

Toru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 172mm² 32Gb MLC NAND flash memory in 34nm CMOS.

Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009