Sizhen Li
Orcid: 0000-0001-7807-5748
According to our database1,
Sizhen Li
authored at least 17 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive V<sub>GS</sub> Control.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A 0.011%/V LS and -76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load.
IEICE Electron. Express, 2024
Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response.
IEICE Electron. Express, 2024
2023
CoRR, 2023
2022
A 23-pW NMOS-Only Voltage Reference With Optimum Body Selection for Process Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
LinearCoFold and LinearCoPartition: Linear-Time Algorithms for Secondary Structure Prediction of Interacting RNA molecules.
CoRR, 2022
CoRR, 2022
2021
LinearTurboFold: Linear-time global prediction of conserved structures for RNA homologs with applications to SARS-CoV-2.
Proc. Natl. Acad. Sci. USA, 2021
2020
A compact hybrid envelope tracking supply modulator with wide-band high-slew-rate linear amplifier.
IEICE Electron. Express, 2020
2018
Proceedings of the First Workshop on Fact Extraction and VERification, 2018
2017
Design Considerations of Charge Pump for Antenna Switch Controller With SOI CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2010
Microelectron. J., 2010
2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008