Size Zheng

According to our database, Size Zheng authored at least 17 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition.

Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Atom: Low-Bit Quantization for Efficient and Accurate LLM Serving.

Yilong Zhao, Chien-Yu Lin, Kan Zhu, Zihao Ye, Lequn Chen, Size Zheng, Luis Ceze, Arvind Krishnamurthy, Tianqi Chen, Baris Kasikci

Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024

vMCU: Coordinated Memory Management and Kernel Optimization for DNN Inference on MCUs.

Size Zheng, Renze Chen, Meng Li, Zihao Ye, Luis Ceze, Yun Liang

Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024

SpREM: Exploiting Hamming Sparsity for Fast Quantum Readout Error Mitigation.

Hanyu Zhang, Liqiang Lu, Siwei Tan, Size Zheng, Jia Yu, Jianwei Yin

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices.

Renze Chen, Zijian Ding, Size Zheng, Meng Li, Yun Liang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

SpecPIM: Accelerating Speculative Inference on PIM-Enabled System via Architecture-Dataflow Co-Exploration.

Cong Li, Zhe Zhou, Size Zheng, Jiaxi Zhang, Yun Liang, Guangyu Sun

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

MAGIS: Memory Optimization via Coordinated Graph Transformation and Scheduling for DNN.

Renze Chen, Zijian Ding, Size Zheng, Chengrui Zhang, Jingwen Leng, Xuanzhe Liu, Yun Liang

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis.

Size Zheng, Siyuan Chen, Siyuan Gao, Liancheng Jia, Guangyu Sun, Runsheng Wang, Yun Liang

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions.

Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Chimera: An Analytical Optimizing Framework for Effective Compute-intensive Operators Fusion.

Size Zheng, Siyuan Chen, Peidi Song, Renze Chen, Xiuhong Li, Shengen Yan, Dahua Lin, Jingwen Leng, Yun Liang

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Memory and Computation Coordinated Mapping of DNNs onto Complex Heterogeneous SoC.

Size Zheng, Siyuan Chen, Yun Liang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition.

Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

NeoFlow: A Flexible Framework for Enabling Efficient Compilation for High Performance DNN Training.

Size Zheng, Renze Chen, Yicheng Jin, Anjiang Wei, Bingyang Wu, Xiuhong Li, Shengen Yan, Yun Liang

IEEE Trans. Parallel Distributed Syst., 2022

AMOS: enabling automatic mapping for tensor computations on spatial accelerators with hardware abstraction.

Size Zheng, Renze Chen, Anjiang Wei, Yicheng Jin, Qin Han, Liqiang Lu, Bingyang Wu, Xiuhong Li, Shengen Yan, Yun Liang

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation.

Qingcheng Xiao, Size Zheng, Bingzhe Wu, Pengcheng Xu, Xuehai Qian, Yun Liang

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.

Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System.

Size Zheng, Yun Liang, Shuo Wang, Renze Chen, Kaiwen Sheng

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020