Siwan Dong
Orcid: 0000-0002-1598-006X
According to our database1,
Siwan Dong
authored at least 17 papers
between 2015 and 2025.
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2024
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Bibliography
2025
A small area-occupation three-stage OTA with transistor resistance and parasitic capacitance Q-factor modulation for miniaturized communication systems.
Microelectron. J., 2025
2024
A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording.
Microelectron. J., 2024
An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS.
Microelectron. J., 2024
2023
A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs.
Circuits Syst. Signal Process., August, 2023
A 0.6-1.8 V/0.4-1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes.
Circuits Syst. Signal Process., 2023
A sharpened reconfigurable CIC filter for multi-channel human-computer interaction data sampling.
Proceedings of the 6th International Conference on Artificial Intelligence and Pattern Recognition, 2023
2022
A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique.
Microelectron. J., 2022
A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference.
Circuits Syst. Signal Process., 2022
2021
A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration.
Microelectron. J., 2021
A three-stage OTA with hybrid active miller enhanced compensation technique for large to heavy load applications.
Microelectron. J., 2021
A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications.
Circuits Syst. Signal Process., 2021
2020
A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS.
IEEE Access, 2020
2019
Circuits Syst. Signal Process., 2019
2018
Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM.
Microelectron. J., 2018
A transconductance-enhancement cascode Miller compensation for low-power multistage amplifiers.
Microelectron. J., 2018
2015
Microelectron. J., 2015
J. Circuits Syst. Comput., 2015