Siva Satyendra Sahoo
Orcid: 0000-0002-2243-5350
According to our database1,
Siva Satyendra Sahoo
authored at least 32 papers
between 2016 and 2024.
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Online presence:
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on orcid.org
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
<i>AxOMaP</i>: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming.
ACM Trans. Reconfigurable Technol. Syst., June, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Enabling Energy-efficient AI Computing: Leveraging Application-specific Approximations : (Education Class).
Proceedings of the International Conference on Compilers, 2024
2023
IEEE Embed. Syst. Lett., December, 2023
<i>AxOTreeS</i>: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators.
ACM Trans. Embed. Comput. Syst., October, 2023
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming.
CoRR, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
<i>AppAxO</i>: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Computers, 2021
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.
IEEE Access, 2021
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
<i>MemOReL</i>: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives.
Proceedings of the CODES/ISSS 2021, 2021
2020
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems.
Integr., 2019
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016