Siva Sankar Yellampalli

According to our database, Siva Sankar Yellampalli authored at least 23 papers between 2003 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

RadiomixNet: Integrating Radiomics and Feature Extraction for Advanced Pneumonia Diagnosis.

Rahul Gowtham Poola, Siva Sankar Yellampalli

IEEE Access, 2025

2024

SyntDiaNet: Integrating feature extraction, transfer learning and classifier-embedded generative adversarial network for advanced pneumonia diagnosis.

Rahul Gowtham Poola, P. L. Lahari, Siva Sankar Yellampalli

Multim. Tools Appl., August, 2024

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices.

Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Survey of PCB Defect Detection Algorithms.

Gayathri Lakshmi, V. Udaya Sankar, Y. Siva Sankar

J. Electron. Test., December, 2023

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks.

Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi

Microelectron. J., September, 2023

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design.

Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi

Microelectron. J., March, 2023

2022

Negative capacitance FETs for energy efficient and hardware secure logic designs.

Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi

Microelectron. J., 2022

A Review of Various Defects in PCB.

V. Udaya Sankar, Gayathri Lakshmi, Y. Siva Sankar

J. Electron. Test., 2022

Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks.

Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

GPS and LoRa module Based Safety Alert system.

Parshal Chitrakar, Yoganand Biradavolu, Siva Sankar Yellampalli

Proceedings of the IEEE International Conference on RFID Technology and Applications, 2021

Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators.

P. L. Lahari, Siva Sankar Yellampalli, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Steep Switching NCFET based Logic for Future Energy Efficient Electronics.

Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Smart Agriculture using IoT & Filtering Technology.

Sameeksha Konakalla, Lakshmi Vyshnavi Kunchala, Siva Sankar Yellampalli

Proceedings of the 12th International Conference on Computing Communication and Networking Technologies, 2021

2019

Smart Receivers with Modular and Multifunctional Front-End Blocks: The Benefits of Using Programmable Modulators and Demodulators.

Nanda Kishora Holla, Siva Sankar Yellampalli

IEEE Consumer Electron. Mag., 2019

2015

Analog BIST for Capacitive MEMS Sensor using PLL.

Favoureen Swer, V. Pradeep, Siva Sankar Yellampalli

Proceedings of the Third International Symposium on Women in Computing and Informatics, 2015

Detection and analysis of hardware trojan using scan chain method.

Munishamanna Rithesh, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Low power and hardware cost STUMPS BIST.

N. Ravi Kiran, G. Harish, A. Karthik, Siva Sankar Yellampalli

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Modified low power scan based technique.

M. R. Gowthami, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Design and implementation of sample and hold circuit in 180nm CMOS technology.

Prakruthi T. G., Siva Sankar Yellampalli

Proceedings of the 2015 International Conference on Advances in Computing, 2015

2014

The Design of Ultra Low Power CMOS CGLNA in Nanometer Technology.

P. Kavyashree, Siva Sankar Yellampalli

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Design of power efficient SPI interface.

Dwaraka N. Oruganti, Siva Sankar Yellampalli

Proceedings of the 2014 International Conference on Advances in Computing, 2014

2011

Δ<i>I_DDQ</i> Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects.

Rajiv Soundararajan, Ashok Srivastava, Siva Sankar Yellampalli

Circuits Syst., 2011

2003

Dynamic Mapping in a Heterogeneous Environment with Tasks Having Priorities and Multiple Deadlines.

Jong-Kook Kim, Sameer Shivle, Howard Jay Siegel, Anthony A. Maciejewski, Tracy D. Braun, Myron Schneider, Sonja Tideman, Ramakrishna Chitta, Raheleh B. Dilmaghani, Rohit Joshi, Aditya Kaul, Ashish Sharma, Siddhartha Sripada, Praveen Vangari, Siva Sankar Yellampalli

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003