Sitaraman Iyer
According to our database1,
Sitaraman Iyer
authored at least 5 papers
between 2010 and 2024.
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Bibliography
2024
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2010
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010