Sitaraman Iyer

According to our database1, Sitaraman Iyer authored at least 5 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2020
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2018
SkyLake-SP: A 14nm 28-Core xeon® processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2010
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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