Sirisha Rani Kale

According to our database, Sirisha Rani Kale authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.

Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

IEEE J. Solid State Circuits, April, 2024

2021

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits.

Jongseok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juarez Hernandez, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano

IEEE J. Solid State Circuits, 2021

A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology.

Jong Seok Park, Sushil Subramanian, Lester Lampert, Todor Mladenov, Ilya Klotchkov, Dileep Kurian, Esdras Juárez-Hernández, Brando Perez Esparza, Sirisha Rani Kale, K. T. Asma Beevi, Shavindra P. Premaratne, Thomas Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, Stefano Pellerano

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding.

Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Dileep Kurian, Indranil Chakraborty, Sirisha Rani Kale, Nilesh Jain, Tanay Karnik, Ravi R. Iyer, Anuradha Srinivasan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021