Simone Secchi
Orcid: 0000-0002-9307-1347
According to our database1,
Simone Secchi
authored at least 24 papers
between 2004 and 2019.
Collaborative distances:
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Bibliography
2019
Symmetry, 2019
2017
Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures.
IEEE Trans. Parallel Distributed Syst., 2017
2015
Special Issue on Architectures and Algorithms for Irregular Applications (AAIA) - Guest editors' introduction.
J. Parallel Distributed Comput., 2015
2013
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013
Exploring manycore multinode systems for irregular applications with FPGA prototyping.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
VLSI Design, 2012
IEEE Trans. Parallel Distributed Syst., 2012
Designing Next-Generation Massively Multithreaded Architectures for Irregular Applications.
Computer, 2012
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012
2011
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011
Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT.
Proceedings of the 11th IEEE/ACM International Symposium on Cluster, 2011
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
2010
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures.
IEEE Embed. Syst. Lett., 2010
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.
Proceedings of the Embedded Computer Systems: Architectures, 2008
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007
2004
Appl. Math. Lett., 2004