Simon W. Moore

According to our database, Simon W. Moore authored at least 90 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.

Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore

IEEE Des. Test, February, 2024

CHERI: Hardware-Enabled C/C++ Memory Protection at Scale.

Robert N. M. Watson, David Chisnall, Jessica Clarke, Brooks Davis, Nathaniel Wesley Filardo, Ben Laurie, Simon W. Moore, Peter G. Neumann, Alexander Richardson, Peter Sewell, Konrad Witaszczyk, Jonathan Woodruff

IEEE Secur. Priv., 2024

Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety.

Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Jessica Clarke, Peter Rugg, Brooks Davis, Mark Johnston, Robert M. Norton, David Chisnall, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

How Flexible Is CXL's Memory Protection?

Samuel W. Stark, A. Theodore Markettos, Simon W. Moore

Commun. ACM, December, 2023

POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.

Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming

ACM Trans. Parallel Comput., June, 2023

How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel.

Samuel W. Stark, A. Theodore Markettos, Simon W. Moore

ACM Queue, 2023

The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System.

Richard Grisenthwaite, Graeme Barnes, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Jonathan Woodruff

IEEE Micro, 2023

CHERIoT: Complete Memory Safety for Embedded Devices.

Saar Amar, David Chisnall, Tony Chen, Nathaniel Wesley Filardo, Ben Laurie, Kunyan Liu, Robert M. Norton, Simon W. Moore, Yucong Tao, Robert N. M. Watson, Hongyan Xia

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Towards xBGAS on CHERI: Supporting a Secure Global Memory.

Mert Side, Brody Williams, John D. Leidel, Jonathan Woodruff, Simon W. Moore, Yong Chen

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Architectural Contracts for Safe Speculation.

Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022

Practical Distributed Implementation of Very Large Scale Petri Net Simulations.

Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown

Trans. Petri Nets Other Model. Concurr., 2022

Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.

Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown

IET Comput. Digit. Tech., 2022

CompartOS: CHERI Compartmentalization for Embedded Systems.

Hesham Almatary, Michael Dodson, Jessica Clarke, Peter Rugg, Ivan Gomes, Michal Podhradsky, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson

CoRR, 2022

Non-deterministic event brokered computing.

Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev

Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

2021

General hardware multicasting for fine-grained message-passing architectures.

Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2020

Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.

Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell

Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

Cornucopia: Temporal Safety for CHERI Heaps.

Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson

Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

Position Paper: Defending Direct Memory Access with CHERI Capabilities.

A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson

Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation.

Marno van der Maas, Simon W. Moore

Proceedings of the CYSARM@CCS '20: Proceedings of the 2nd Workshop on Cyber-Security Arms Race, 2020

Termination detection for fine-grained message-passing architectures.

Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

CHERI Concentrate: Practical Compressed Capabilities.

Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony C. J. Fox, Robert M. Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel Wesley Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore

IEEE Trans. Computers, 2019

Through computer architecture, darkly.

A. Theodore Markettos, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Peter G. Neumann

Commun. ACM, 2019

Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals.

A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson

Proceedings of the 26th Annual Network and Distributed System Security Symposium, 2019

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety.

Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel Wesley Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, Timothy M. Jones

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Tinsel: A Manythread Overlay for FPGA Clusters.

Matthew Naylor, Simon W. Moore, David B. Thomas

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment.

Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, Jessica Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Jonathan Woodruff

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

CheriRTOS: A Capability Model for Embedded Devices.

Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017

Programming Model to Develop Supercomputer Combinatorial Solvers.

Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew D. Brown

Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

Efficient Tagged Memory.

Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

CHERI JNI: Sinking the Java Security Model into the C.

David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert M. Norton, Stacey D. Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N. M. Watson

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture.

Robert N. M. Watson, Robert M. Norton, Jonathan Woodruff, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Michael Roe, Nirav H. Dave, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Ed Maste, Steven J. Murdoch, Colin Rothwell, Stacey D. Son, Munraj Vadera

IEEE Micro, 2016

CHERI: A Hardware-Software System to Support the Principle of Least Privilege.

Robert N. M. Watson, Simon W. Moore, Peter G. Neumann

ERCIM News, 2016

A consistency checker for memory subsystem traces.

Matthew Naylor, Simon W. Moore, Alan Mujumdar

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs.

A. Theodore Markettos, Simon W. Moore, Brian D. Jones, Roy Spliet, Vlad A. Gavrila

Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015

CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization.

Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav H. Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert M. Norton, Michael Roe, Stacey D. Son, Munraj Vadera

Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

A generic synthesisable test bench.

Matthew Naylor, Simon W. Moore

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine.

David Chisnall, Colin Rothwell, Robert N. M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Michael Roe, Brooks Davis, Peter G. Neumann

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Power Optimized Transceivers for Future Switched Networks.

Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore, Andrew W. Moore

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reliably prototyping large SoCs using FPGA clusters.

Paul James Fox, A. Theodore Markettos, Simon W. Moore

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

The CHERI capability model: Revisiting RISC in an age of risk.

Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert M. Norton, Michael Roe

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Rapid codesign of a soft vector processor and its compiler.

Matthew Naylor, Simon W. Moore

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Interconnect for commodity FPGA clusters: Standardized or customized?

A. Theodore Markettos, Paul James Fox, Simon W. Moore, Andrew W. Moore

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors.

Christian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore

IEEE Trans. Computers, 2013

A 64-bit MIPS processor running freebsd on a portable FPGA tablet.

Jonathan Woodruff, A. Theodore Markettos, Simon W. Moore

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Managing the FPGA memory wall: Custom computing or vector processing?

Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A spiking neural network on a portable FPGA tablet.

Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Energy Implications of Photonic Networks With Speculative Transmission.

Philip M. Watts, Simon W. Moore, Andrew W. Moore

JOCN, 2012

Mamba: A scalable communication centric multi-threaded processor architecture.

Gregory A. Chadwick, Simon W. Moore

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation.

Simon W. Moore, Paul James Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2010

Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits.

Danielle S. Bassett, Daniel Greenfield, Andreas Meyer-Lindenberg, Daniel R. Weinberger, Simon W. Moore, Edward T. Bullmore

PLoS Comput. Biol., 2010

Proximity coherence for chip multiprocessors.

Nick Barrow-Williams, Christian Fensch, Simon W. Moore

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

An Energy and Performance Exploration of Network-on-Chip Architectures.

Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit

IEEE Trans. Very Large Scale Integr. Syst., 2009

Implications of Electronics Technology Trends for Algorithm Design.

Daniel Greenfield, Simon W. Moore

Comput. J., 2009

Flow-aware allocation for on-chip networks.

Arnab Banerjee, Simon W. Moore

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A communication characterisation of Splash-2 and Parsec.

Nick Barrow-Williams, Christian Fensch, Simon W. Moore

Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.

Rosemary M. Francis, Simon W. Moore

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators.

A. Theodore Markettos, Simon W. Moore

Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008

Fractal communication in software data dependency graphs.

Daniel Greenfield, Simon W. Moore

Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

The next resource war: computation vs. communication.

Simon W. Moore, Daniel Greenfield

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

A Network of Time-Division Multiplexed Wiring for FPGAs.

Rosemary M. Francis, Simon W. Moore, Robert D. Mullins

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Exploring hard and soft networks-on-chip for FPGAs.

Rosemary M. Francis, Simon W. Moore

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Tamper Protection for Security Devices.

Philip Christopher Paul, Simon W. Moore, Simon W.-B. Tam

Proceedings of the 2008 ECSIS Symposium on Bio-inspired, 2008

Implications of Electronics Technology Trends to Algorithm Design.

Daniel Greenfield, Simon W. Moore

Proceedings of the Visions of Computer Science, 2008

2007

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.

Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Power and Energy Exploration of Network-on-Chip Architectures.

Arnab Banerjee, Robert D. Mullins, Simon W. Moore

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Demystifying Data-Driven and Pausible Clocking Schemes.

Robert D. Mullins, Simon W. Moore

Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006

An Asynchronous Interconnect Architecture for Device Security Enhancement.

Simon Hollis, Simon W. Moore

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Adding question answering to an e-tutor for programming languages.

Kate Taylor, Simon W. Moore

Proceedings of the Applications and Innovations in Intelligent Systems XIV, 2006

An area-efficient, pulse-based interconnect.

Simon Hollis, Simon W. Moore

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

RasP: An Area-efficient, On-chip Network.

Simon Hollis, Simon W. Moore

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

An Asynchronous PLA with Improved Security Characteristics.

Petros Oikonomakos, Simon W. Moore

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography.

Jacques J. A. Fournier, Simon W. Moore

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Implementing Cryptography on TFT Technology for Secure Display Applications.

Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore

Proceedings of the Smart Card Research and Advanced Applications, 2006

The design and implementation of a low-latency on-chip network.

Robert D. Mullins, Andrew West, Simon W. Moore

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

My Compiler Really Understands Me: An Adaptive Programming Language Tutor.

Kate Taylor, Simon W. Moore

Proceedings of the Adaptive Hypermedia and Adaptive Web-Based Systems, 2006

2005

A Vector Approach to Cryptography Implementation.

Jacques J. A. Fournier, Simon W. Moore

Proceedings of the Digital Rights Management: Technologies, 2005

Security Evaluation Against Electromagnetic Analysis at Design Time.

Huiyun Li, A. Theodore Markettos, Simon W. Moore

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

Self-Timed Circuitry for Global Clocking.

Scott Fairbanks, Simon W. Moore

Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004

Low-Latency Virtual-Channel Routers for On-Chip Networks.

Robert D. Mullins, Andrew West, Simon W. Moore

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Analog Micropipeline Rings for High Precision Timing.

Scott Fairbanks, Simon W. Moore

Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003

Balanced self-checking asynchronous logic for smart card applications.

Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier

Microprocess. Microsystems, 2003

Security Evaluation of Asynchronous Circuits.

Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor

Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002

JMA: The Java-Multithreading Architecture for Embedded Processors.

Panit Watcharawitch, Simon W. Moore

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Point to Point GALS Interconnect.

George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Improving Smart Card Security Using Self-Timed Circuits.

Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001

Protecting Consumer Security Devices.

Simon W. Moore

Proceedings of the Smart Card Programming and Security, 2001

2000

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.

Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.

George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998

Rapid prototyping of self-timed circuits.

Simon W. Moore, Peter Robinson

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1995

Tagged Up/Down Sorter - A Hardware Priority Queue.

Simon W. Moore, Brian T. Graham

Comput. J., 1995