Simon M. Tam

According to our database, Simon M. Tam authored at least 23 papers between 1992 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

SkyLake-SP: A 14nm 28-Core xeon® processor.

Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015

Low-Cost On-Chip Clock Jitter Measurement Scheme.

Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam

IEEE Trans. Very Large Scale Integr. Syst., 2015

A 22 nm 15-Core Enterprise Xeon® Processor Family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

IEEE J. Solid State Circuits, 2015

2014

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.

Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation.

Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

New Design for Testability Approach for Clock Fault Testing.

Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam

IEEE Trans. Computers, 2012

2011

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors.

Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

A 45 nm 8-Core Enterprise Xeon¯ Processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

IEEE J. Solid State Circuits, 2010

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter.

Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

A 45nm 8-core enterprise Xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Power reduction techniques for an 8-core xeon® processor.

Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.

Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora

IEEE J. Solid State Circuits, 2007

Novel Approach to Clock Fault Testing for High Performance Microprocessors.

Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Novel compensation scheme for local clocks of high performance microprocessors.

Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache.

Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 130-nm triple-V_t 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.

Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni

IEEE J. Solid State Circuits, 2005

2004

Clock generation and distribution for the 130-nm Itanium^® 2 processor with 6-MB on-die L3 cache.

Simon Tam, Rahul Dilip Limaye, Utpal Nagarji Desai

IEEE J. Solid State Circuits, 2004

2003

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.

Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer

IEEE J. Solid State Circuits, 2003

2000

Clock generation and distribution for the first IA-64 microprocessor.

Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young

IEEE J. Solid State Circuits, 2000

Itanium processor clock design.

Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu

Proceedings of the 2000 International Symposium on Physical Design, 2000

1992

Analog VLSI neural networks for impact signal processing.

Jeff Brauch, Simon M. Tam, Mark A. Holler, Arthur L. Shmurun

IEEE Micro, 1992