Simon J. Hollis
According to our database1,
Simon J. Hollis
authored at least 20 papers
between 2009 and 2019.
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Bibliography
2019
A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2016
Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Overview of Swallow - A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems.
CoRR, 2015
Comput. J., 2015
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015
2014
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip.
IET Comput. Digit. Tech., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 2014 International Conference on Compilers, 2014
2013
CoRR, 2013
2012
CoRR, 2012
2011
Microprocess. Microsystems, 2011
Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs.
Int. J. Embed. Real Time Commun. Syst., 2011
Proceedings of the 33th Communicating Process Architectures Conference, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009