Simon J. Bale
Orcid: 0000-0002-3361-5648
According to our database1,
Simon J. Bale
authored at least 25 papers
between 2013 and 2024.
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Bibliography
2024
Design and Application of RFIC Detector: To Measure Coupled Power into IC Pin via PCB Trace.
Proceedings of the 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2024
2023
Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow.
IET Comput. Digit. Tech., 2023
2022
Proceedings of the International Joint Conference on Neural Networks, 2022
2021
Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Multi-objective Digital Design Optimisation via Improved Drive Granularity Standard Cells.
CoRR, 2021
Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow.
CoRR, 2021
Adaptive Integer Quantisation for Convolutional Neural Networks through Evolutionary Algorithms.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021
2019
Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs.
IET Comput. Digit. Tech., 2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
2018
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018
2017
Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device.
IEEE Trans. Computers, 2017
An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2015
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration.
IET Comput. Digit. Tech., 2015
Two-phase multiobjective genetic algorithm for constrained circuit clustering on FPGAs.
Proceedings of the IEEE Congress on Evolutionary Computation, 2015
2014
Circuit design optimisation using a modified genetic algorithm and device layout motifs.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
Evolving hierarchical low disruption fault tolerance strategies for a novel programmable device.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
Optimising ring oscillator frequency on a novel FPGA device via partial reconfiguration.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014
Proceedings of the IEEE Congress on Evolutionary Computation, 2014
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014
2013
IEEE Trans. Computers, 2013
Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations.
Proceedings of the 2013 IEEE International Conference on Evolvable Systems, 2013
Proceedings of the IEEE Congress on Evolutionary Computation, 2013