Simi Zerine Sleeba

Orcid: 0000-0002-2716-270X

According to our database1, Simi Zerine Sleeba authored at least 11 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2024
Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip.
J. Circuits Syst. Comput., August, 2024

2022
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Traffic aware routing in 3D NoC using interleaved asymmetric edge routers.
Nano Commun. Networks, 2021

2019
2L-2D Routing for Buffered Mesh Network-on-Chip.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip.
Proceedings of the TENCON 2019, 2019

Asymmetric routing in 3D NoC using interleaved edge routers.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018
Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips.
IET Comput. Digit. Tech., 2018

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017
An enhanced model for reliable deflection routing in mesh network on chip.
Int. J. High Perform. Syst. Archit., 2017

2014
WeDBless: weighted deflection bufferless router for mesh NoCs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014


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