Siji Huang
Orcid: 0000-0001-5296-6235
According to our database1,
Siji Huang
authored at least 10 papers
between 2011 and 2024.
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Bibliography
2024
The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024
An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2018
An Output-Capacitorless Adaptively Biased Low-Dropout Regulator with Maximum 132-MHz UGF and Without Minimum Loading Requirement.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2012
Adaptive Polar-Linear Interpolation Aided Channel Estimation for Wireless Communication Systems.
IEEE Trans. Wirel. Commun., 2012
2011
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011