Sigang Ryu
Orcid: 0000-0001-5307-8117
According to our database1,
Sigang Ryu
authored at least 7 papers
between 2012 and 2024.
Collaborative distances:
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Bibliography
2024
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2018
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2016
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012