Siew-Kei Lam

Orcid: 0000-0002-8346-2635

Affiliations:
  • Nanyang Technological University (NTU), School of Computer Science and Engineering, Singapore


According to our database1, Siew-Kei Lam authored at least 182 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Layer Sequence Extraction of Optimized DNNs Using Side-Channel Information Leaks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Share-Aware Joint Model Deployment and Task Offloading for Multi-Task Inference.
IEEE Trans. Intell. Transp. Syst., June, 2024

A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.
Sensors, May, 2024

Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots.
Sensors, March, 2024

Employing feature mixture for active learning of object detection.
Neurocomputing, 2024

Hardware Accelerator for Feature Matching with Binary Search Tree.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Streamlining DNN Obfuscation to Defend Against Model Stealing Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Graph Mining under Data scarcity.
Proceedings of the International Joint Conference on Neural Networks, 2024

Achieving Real-time Visual Tracking with Low-Cost Edge AI.
Proceedings of the 15th ACM/IEEE International Conference on Cyber-Physical Systems, 2024

GPSFormer: A Global Perception and Local Structure Fitting-Based Transformer for Point Cloud Understanding.
Proceedings of the Computer Vision - ECCV 2024, 2024

2023
CoTree: A Side-Channel Collision Tool to Push the Limits of Conquerable Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

A Versatile Approach to Polygonal Object Avoidance in Indoor Environments with Hardware Schemes Using an FPGA-Based Multi-Robot.
Sensors, December, 2023

Two-Level Scheduling Algorithms for Deep Neural Network Inference in Vehicular Networks.
IEEE Trans. Intell. Transp. Syst., September, 2023

Blockchain-Based Secure Key Management for Mobile Edge Computing.
IEEE Trans. Mob. Comput., 2023

Hardware-Efficient Scheme for Trailer Robot Parking by Truck Robot in an Indoor Environment with Rendezvous.
Sensors, 2023

Computer vision framework for crack detection of civil infrastructure - A review.
Eng. Appl. Artif. Intell., 2023

Training-Free Attentive-Patch Selection for Visual Place Recognition.
IROS, 2023

DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2022
Enhanced Multi-Task Learning Architecture for Detecting Pedestrian at Far Distance.
IEEE Trans. Intell. Transp. Syst., 2022

A Unified Multi-Task Learning Architecture for Fast and Accurate Pedestrian Detection.
IEEE Trans. Intell. Transp. Syst., 2022

Learning Traffic Network Embeddings for Predicting Congestion Propagation.
IEEE Trans. Intell. Transp. Syst., 2022

Fast Semantic-Aware Motion State Detection for Visual SLAM in Dynamic Environment.
IEEE Trans. Intell. Transp. Syst., 2022

A Multi-Scale Attributes Attention Model for Transport Mode Identification.
IEEE Trans. Intell. Transp. Syst., 2022

Exploring Public Transport Transfer Opportunities for Pareto Search of Multicriteria Journeys.
IEEE Trans. Intell. Transp. Syst., 2022

Decoupled self-supervised label augmentation for fully-supervised image classification.
Knowl. Based Syst., 2022

ML-MMAS: Self-learning ant colony optimization for multi-criteria journey planning.
Inf. Sci., 2022

Snowball: Another View on Side-Channel Key Recovery Tools.
IACR Cryptol. ePrint Arch., 2022

Multi-fold Correlation Attention Network for Predicting Traffic Speeds with Heterogeneous Frequency.
Appl. Soft Comput., 2022

Reinforced Continual Learning for Graphs.
Proceedings of the 31st ACM International Conference on Information & Knowledge Management, 2022

2021
Multiple-Differential Mechanism for Collision-Optimized Divide-and-Conquer Attacks.
IEEE Trans. Inf. Forensics Secur., 2021

Information Entropy-Based Leakage Profiling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

SNR-Centric Power Trace Extractors for Side-Channel Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

The Science of Guessing in Collision-Optimized Divide-and-Conquer Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

ACSL: Adaptive correlation-driven sparsity learning for deep neural network compression.
Neural Networks, 2021

Passenger-centric vehicle routing for first-mile transportation considering request uncertainty.
Inf. Sci., 2021

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage.
IACR Cryptol. ePrint Arch., 2021

CoTree: Push the Limits of Conquerable Space in Collision-Optimized Side-Channel Attacks.
IACR Cryptol. ePrint Arch., 2021

CAP: Context-Aware Pruning for Semantic Segmentation.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021

Learning Congestion Propagation Behaviors for Traffic Prediction.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

Hierarchical Loop Closure Detection for Long-term Visual SLAM with Semantic-Geometric Descriptors.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

Predicting Traffic Congestion Evolution: A Deep Meta Learning Approach.
Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

Self-Growing Spatial Graph Network for Context-Aware Pedestrian Trajectory Prediction.
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021

Accelerating Continual Learning on Edge FPGA.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Edge Accelerator for Lifelong Deep Learning using Streaming Linear Discriminant Analysis.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Designing Energy-Efficient MPSoC with Untrustworthy 3PIP Cores.
IEEE Trans. Parallel Distributed Syst., 2020

Group Cost-Sensitive BoostLR With Vector Form Decorrelated Filters for Pedestrian Detection.
IEEE Trans. Intell. Transp. Syst., 2020

Peak-Hour Vehicle Routing for First-Mile Transportation: Problem Formulation and Algorithms.
IEEE Trans. Intell. Transp. Syst., 2020

Hardware Performance Counter-Based Fine-Grained Malware Detection.
ACM Trans. Embed. Comput. Syst., 2020

A First Study of Compressive Sensing for Side-Channel Leakage Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Lightweight Detection Algorithm For Collision-Optimized Divide-and-Conquer Attacks.
IEEE Trans. Computers, 2020

IROS 2019 Lifelong Robotic Vision: Object Recognition Challenge [Competitions].
IEEE Robotics Autom. Mag., 2020

Improving accuracy of HPC-based malware classification for embedded platforms using gradient descent optimization.
J. Cryptogr. Eng., 2020

Learning heterogeneous traffic patterns for travel time prediction of bus journeys.
Inf. Sci., 2020

Graph2Kernel Grid-LSTM: A Multi-Cued Model for Pedestrian Trajectory Prediction by Learning Adaptive Neighborhoods.
CoRR, 2020

IROS 2019 Lifelong Robotic Vision Challenge - Lifelong Object Recognition Report.
CoRR, 2020

Multiple-Choice Hardware/Software Partitioning for Tree Task-Graph on MPSoC.
Comput. J., 2020

Fusing Semantics and Motion State Detection for Robust Visual SLAM.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2020

Self-Growing Spatial Graph Networks for Pedestrian Trajectory Prediction.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2020

Evaluating the Merits of Ranking in Structured Network Pruning.
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020

Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Efficient three-stage auction schemes for cloudlets deployment in wireless access network.
Wirel. Networks, 2019

Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2019

High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Travel-Time Prediction of Bus Journey With Multiple Bus Trips.
IEEE Trans. Intell. Transp. Syst., 2019

Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Data-path unrolling with logic folding for area-time-efficient FPGA-based FAST corner detector.
J. Real Time Image Process., 2019

Algorithms for Reconfiguring NoC-Based Fault-Tolerant Multiprocessor Arrays.
J. Circuits Syst. Comput., 2019

The Art of Guessing in Combined Side-Channel Collision Attacks.
IACR Cryptol. ePrint Arch., 2019

Full Collision Attack: Pushing the Limits of Exhaustible Key Spaces.
IACR Cryptol. ePrint Arch., 2019

Situation-Aware Pedestrian Trajectory Prediction with Spatio-Temporal Attention Model.
CoRR, 2019

Collaborative Task Offloading with Computation Result Reusing for Mobile Edge Computing.
Comput. J., 2019

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Bus Travel Speed Prediction using Attention Network of Heterogeneous Correlation Features.
Proceedings of the 2019 SIAM International Conference on Data Mining, 2019

Revisiting Visual Odometry for Real-Time Performance.
Proceedings of the 16th International Conference on Machine Vision Applications, 2019

Lowering Dynamic Power of a Stream-based CNN Hardware Accelerator.
Proceedings of the 21st IEEE International Workshop on Multimedia Signal Processing, 2019

Predicting Travel Time of Bus Journeys with Alternative Bus Services.
Proceedings of the 2019 International Conference on Data Mining Workshops, 2019

Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

TAD: time side-channel attack defense of obfuscated source code.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Threshold-Guided Design and Optimization for Harris Corner Detector Architecture.
IEEE Trans. Circuits Syst. Video Technol., 2018

Area-Time Efficient FAST Corner Detector Using Data-Path Transposition.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Compressive Sensing based Leakage Sampling and Reconstruction: A First Study.
IACR Cryptol. ePrint Arch., 2018

Information Entropy Based Leakage Certification.
IACR Cryptol. ePrint Arch., 2018

Efficient hybrid multicast approach in wireless data center network.
Future Gener. Comput. Syst., 2018

Algorithms for Replica Placement and Update in Tree Network.
Comput. J., 2018

Automatic Pixel-Level Pavement Crack Detection Using Information of Multi-Scale Neighborhoods.
IEEE Access, 2018

Rapid detection of rowhammer attacks using dynamic skewed hash tree.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Stream-Based ORB Feature Extractor with Dynamic Power Optimization.
Proceedings of the International Conference on Field-Programmable Technology, 2018

CIDPro: Custom Instructions for Dynamic Program Diversification.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Dynamic skewed tree for fast memory integrity verification.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient Sparse to Dense Stereo Matching Technique.
Proceedings of 3rd International Conference on Computer Vision and Image Processing - CVIP 2018, Jabalpur, India, September 29, 2018

Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms.
Proceedings of the PROOFS 2018, 2018

LifeSim: A lifetime reliability simulator for manycore systems.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2017
Joint Charging Tour Planning and Depot Positioning for Wireless Sensor Networks Using Mobile Chargers.
IEEE/ACM Trans. Netw., 2017

A Framework for Fast and Robust Visual Odometry.
IEEE Trans. Intell. Transp. Syst., 2017

Approximate compressed sensing for hardware-efficient image compression.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fast and Accurate Pedestrian Detection using Dual-Stage Group Cost-Sensitive RealBoost with Vector Form Filters.
Proceedings of the 2017 ACM on Multimedia Conference, 2017

QoE-Aware Task Offloading for Time Constraint Mobile Applications.
Proceedings of the 42nd IEEE Conference on Local Computer Networks, 2017

Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

General Algorithm for Fault-Tolerant Virtual Machine Assignments.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Lowering dynamic power in stream-based harris corner detection architecture.
Proceedings of the International Conference on Field Programmable Technology, 2017

Group Cost-sensitive Boosting with Multi-scale Decorrelated Filters for Pedestrian Detection.
Proceedings of the British Machine Vision Conference 2017, 2017

2016
Enhanced low-complexity pruning for corner detection.
J. Real Time Image Process., 2016

Algorithms for bi-objective multiple-choice hardware/software partitioning.
Comput. Electr. Eng., 2016

Real-time road traffic density estimation using block variance.
Proceedings of the 2016 IEEE Winter Conference on Applications of Computer Vision, 2016

Shortest Partial Path First Algorithm for Reconfigurable Processor Array with Faults.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Bounded iterative thresholding for lumen region detection in endoscopic images.
Proceedings of the 14th International Conference on Control, 2016

Reducing Access Latency in Virtual Machine Assignments.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

2015
Algorithmic aspects of graph reduction for hardware/software partitioning.
J. Supercomput., 2015

Nonparametric Technique Based High-Speed Road Surface Detection.
IEEE Trans. Intell. Transp. Syst., 2015

KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Adaptive Window Strategy for High-Speed and Robust KLT Feature Tracker.
Proceedings of the Image and Video Technology - 7th Pacific-Rim Symposium, 2015

Rapid estimation of DSPs utilization for efficient high-level synthesis.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Fast Replica Placement and Update Strategies in Tree Networks.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2014

Parallel reconfiguration algorithms for mesh-connected processor arrays.
J. Supercomput., 2014

Rapid evaluation of custom instruction selection approaches with FPGA estimation.
ACM Trans. Embed. Comput. Syst., 2014

Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control.
J. Low Power Electron., 2014

Algorithmic Aspects for Bi-Objective Multiple-Choice Hardware/Software Partitioning.
Proceedings of the Sixth International Symposium on Parallel Architectures, 2014

Stereo based ROIs generation for detecting pedestrians in close proximity.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

Vision-based pedestrian tracking system using color and motion cue.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Mask-based non-maximal suppression with iterative pruning for low-complexity corner detection.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Automated thresholding for low-complexity corner detection.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Efficient heuristic and tabu search for hardware/software partitioning.
J. Supercomput., 2013

FPGA-aware techniques for rapid generation of profitable custom instructions.
Microprocess. Microsystems, 2013

Iris Recognition Using Stable Dark Features.
J. Comput., 2013

Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Modelling communication overhead for accessing local memories in hardware accelerators.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Iris Recognition of Defocused Images for Mobile phones.
Int. J. Pattern Recognit. Artif. Intell., 2012

Low-complexity pruning for accelerating corner detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Exploiting stable features for iris recognition of defocused images.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Reconfiguration Algorithms for Degradable VLSI Arrays with Switch Faults.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Area-time estimation of C-based functions for design space exploration.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.
IEEE Trans. Computers, 2011

Instruction set customization for area-constrained FPGA designs.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Compiler-assisted technique for rapid performance estimation of FPGA-based processors.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Utilizing Dark Features for Iris Recognition in Less Constrained Environments.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Selecting profitable custom instructions for reconfigurable processors.
J. Syst. Archit., 2010

An efficient edge and corner detector.
Proceedings of the 11th International Conference on Control, 2010

Performance estimation framework for FPGA-based processors.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Accelerating shortest path computations in hardware.
Proceedings of the IEEE Conference on Automation Science and Engineering, 2010

Architecture-Aware Custom Instruction Generation for Reconfigurable Processors.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.
IEEE Trans. Ind. Electron., 2009

Rapid design of area-efficient custom instructions for reconfigurable embedded processing.
J. Syst. Archit., 2009

Run-time management of custom instructions on a partially reconfigurable architecture.
Int. J. Inf. Commun. Technol., 2009

Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Rapid design exploration framework for application-aware customization of soft core processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009

2008
A Short Course on Implementing FPGA Based Digital Systems.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

2007
Rapid Area-Time Estimation Technique for Porting C-based Applications onto FPGA platforms.
Scalable Comput. Pract. Exp., 2007

Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Rapid generation of custom instructions using predefined dataflow structures.
Microprocess. Microsystems, 2006

Efficient Architectures for Segmentation of Endoscopic Images in Micro-Robotic Auto Navigation Systems.
Int. J. Humanoid Robotics, 2006

Efficient management of custom instructions for run-time reconfigurable instruction set processors.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Energy Efficient Cache Tuning with Performance Bound.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
VLSI-efficient schemes for high-speed construction of tangent graph.
Robotics Auton. Syst., 2005

Morphable Structures for Reconfigurable Instruction Set Processors.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction.
IEEE Trans. Ind. Electron., 2004

Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System.
IEEE Trans. Computers, 2004

High-throughput image rotation using sign-prediction based redundant cordic algorithm.
Proceedings of the 2004 International Conference on Image Processing, 2004

2003
Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Architectural design and analysis toolbox to implement shortest path algorithms in hardware.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Low cost logarithmic techniques for high-precision computations.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A linear approximation based hybrid approach for binary logarithmic conversion.
Microprocess. Microsystems, 2002

Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method.
J. Intell. Robotic Syst., 2002

Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction.
Proceedings of the 5th IEEE Southwest Symposium on Image Analysis and Interpretation, 2002

An efficient architecture for adaptive progressive thresholding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Fuzzy-ART based image compression for hardware implementation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Incorporating area-time flexibility to a binary signed-digit adder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
High-Speed Environment Representation Scheme for Dynamic Path Planning.
J. Intell. Robotic Syst., 2001

2000
VLSI based hardware accelerator for compute intensive routing applications
PhD thesis, 2000

Dynamic multicast routing in VLSI.
Comput. Commun., 2000


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