Sidharth Rao

Orcid: 0000-0001-6161-3052

According to our database1, Sidharth Rao authored at least 8 papers between 2018 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs.
Proceedings of the IEEE International Test Conference, 2023

Device-Aware Test for Back-Hopping Defects in STT-MRAMs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
SOT-MRAM 300mm integration for low power and ultrafast embedded memories.
CoRR, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.
Proceedings of the IEEE International Reliability Physics Symposium, 2018


  Loading...