Siddhartha Raman Sundara Raman

According to our database, Siddhartha Raman Sundara Raman authored at least 5 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks.

Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni

ACM Trans. Archit. Code Optim., June, 2024

SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture.

Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2022

Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems.

Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni

IEEE J. Solid State Circuits, 2022

Enabling In-Memory Computations in Non-Volatile SRAM Designs.

Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors.

Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021