Siddhartha Nath

According to our database, Siddhartha Nath authored at least 35 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation.

Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, Sung Kyu Lim

ACM Trans. Design Autom. Electr. Syst., July, 2023

BufFormer: A Generative ML Framework for Scalable Buffering.

Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper).

Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TransSizer: A Novel Transformer-Based Fast Gate Sizer.

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Generative self-supervised learning for gate sizing: invited.

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes.

Siddhartha Nath, Vishal Khandelwal

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.

Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning.

Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning.

Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

A Fast Learning-Driven Signoff Power Optimization Framework.

Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2017

Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.

Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath

ACM Trans. Design Autom. Electr. Syst., 2017

2016

New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design.

Siddhartha Nath

PhD thesis, 2016

BEOL stack-aware routability prediction from placement using data mining techniques.

Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Learning-based prediction of embedded memory timing failures during initial floorplan design.

Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Optimization of Overdrive Signoff in High-Performance and Low-Power ICs.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park

IEEE Trans. Very Large Scale Integr. Syst., 2015

ORION3.0: A Comprehensive NoC Router Estimation Tool.

Andrew B. Kahng, Bill Lin, Siddhartha Nath

IEEE Embed. Syst. Lett., 2015

SI for free: machine learning of interconnect coupling delay and transition effects.

Andrew B. Kahng, Mulong Luo, Siddhartha Nath

Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Toward Metrics of Design Automation Research Impact.

Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction.

Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee

Proceedings of the 52nd Annual Design Automation Conference, 2015

3DIC benefit estimation and implementation guidance from 2DIC implementation.

Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Methodology for electromigration signoff in the presence of adaptive voltage scaling.

Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

Optimal reliability-constrained overdrive frequency selection in multicore systems.

Andrew B. Kahng, Siddhartha Nath

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap.

Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap.

Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

OCV-aware top-level clock tree optimization.

Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A deep learning methodology to proliferate golden signoff timing.

Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

High-dimensional metamodeling for prediction of clock tree synthesis outcomes.

Andrew B. Kahng, Bill Lin, Siddhartha Nath

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Learning-based approximation of interconnect delay and slew in signoff timing tools.

Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Incremental multiple-scan chain ordering for ECO flip-flop insertion.

Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Enhanced metamodeling techniques for high-dimensional IC design estimation problems.

Andrew B. Kahng, Bill Lin, Siddhartha Nath

Proceedings of the Design, Automation and Test in Europe, 2013

On potential design impacts of electromigration awareness.

Andrew B. Kahng, Siddhartha Nath, Tajana Rosing

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Optimization of overdrive signoff.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Redefining the Role of the CPU in the Era of CPU-GPU Integration.

Manish Arora, Siddhartha Nath, Subhra Mazumdar, Scott B. Baden, Dean M. Tullsen

IEEE Micro, 2012

Explicit modeling of control and data for improved NoC router estimation.

Andrew B. Kahng, Bill Lin, Siddhartha Nath

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future.

Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Vikram Bhatt, Jonathan Babb, Steven Swanson, Michael B. Taylor

IEEE Micro, 2011