Siddharth Joshi
Orcid: 0000-0002-9201-9678Affiliations:
- University of Notre Dame, Department of Electrical Engineering, IN, USA
- University of California, San Diego, Department of Electrical and Computer Engineering, Jacobs School of Engineering, Institute of Neural Computation, USA
- University of California, San Diego, USA (PhD 2017)
According to our database1,
Siddharth Joshi
authored at least 51 papers
between 2012 and 2024.
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Bibliography
2024
A Remedy to Compute-in-Memory with Dynamic Random Access Memory: 1FeFET-1C Technology for Neuro-Symbolic AI.
CoRR, 2024
Slax: A Composable JAX Library for Rapid and Flexible Prototyping of Spiking Neural Networks.
CoRR, 2024
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Proceedings of the International Conference on Neuromorphic Systems, 2024
2023
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities.
Proc. IEEE, June, 2023
The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
CoRR, 2023
CoRR, 2023
Augmenting Hessians with Inter-Layer Dependencies for Mixed-Precision Post-Training Quantization.
CoRR, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
Mixed Precision Post Training Quantization of Neural Networks with Sensitivity Guided Search.
CoRR, 2023
2022
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
2021
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.
CoRR, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the International Conference on Neuromorphic Systems, 2020
A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver.
Proceedings of the International Conference on Neuromorphic Systems, 2020
A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Sub-µV<sub>rms</sub>-Noise Sub-µW/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging.
IEEE J. Solid State Circuits, 2018
A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
PhD thesis, 2017
Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.
IEEE Trans. Neural Networks Learn. Syst., 2017
21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppression.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation.
IEEE J. Solid State Circuits, 2016
Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link.
IEEE J. Solid State Circuits, 2016
Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses.
CoRR, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
A 6μW/MHz charge buffer with 7fF input capacitance in 65nm CMOS for non-contact electropotential sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link.
Proceedings of the Symposium on VLSI Circuits, 2014
A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
A 12.6 mW 8.3 Mevents/s contrast detection 128×128 imager with 75 dB intra-scene DR asynchronous random-access digital readout.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2012
Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012