Siddharth Garg

Soumya Dutta

IEEE Trans. Vis. Comput. Graph., January, 2025

2024

Manipulation Attacks on Learned Image Compression.

[BibT_eX]

[DOI]

IEEE Trans. Artif. Intell., June, 2024

VeriGen: A Large Language Model for Verilog Code Generation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., May, 2024

Split Computing With Scalable Feature Compression for Visual Analytics on the Edge.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2024

Hyper-parameter Tuning for Fair Classification without Sensitive Attribute Access.

[BibT_eX]

[DOI]

Trans. Mach. Learn. Res., 2024

Privacy-Preserving Collaborative Learning Through Feature Extraction.

[BibT_eX]

[DOI]

Alireza Sarmadi

IEEE Trans. Dependable Secur. Comput., 2024

EMMA: Efficient Visual Alignment in Multi-Modal LLMs.

[BibT_eX]

[DOI]

Sara Ghazanfari

Alexandre Araujo

CoRR, 2024

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search.

[BibT_eX]

[DOI]

Jitendra Bhandari

CoRR, 2024

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.

[BibT_eX]

[DOI]

CoRR, 2024

C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?

[BibT_eX]

[DOI]

Luca Collini

CoRR, 2024

NYU CTF Dataset: A Scalable Open-Source Benchmark Dataset for Evaluating LLMs in Offensive Security.

[BibT_eX]

[DOI]

CoRR, 2024

Model Cascading for Code: Reducing Inference Costs with Model Cascading for LLM Based Code Generation.

[BibT_eX]

[DOI]

CoRR, 2024

Learning-Based Compress-and-Forward Schemes for the Relay Channel.

[BibT_eX]

[DOI]

CoRR, 2024

Evaluating LLMs for Hardware Design and Test.

[BibT_eX]

[DOI]

CoRR, 2024

An Empirical Evaluation of LLMs for Solving Offensive Security Challenges.

[BibT_eX]

[DOI]

CoRR, 2024

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS.

[BibT_eX]

[DOI]

Matthew DeLorenzo

Jeyavijayan Rajendran

CoRR, 2024

Neural Compress-and-Forward for the Relay Channel.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2024

Learned Pulse Shaping Design for PAPR Reduction in DFT-s-OFDM.

[BibT_eX]

[DOI]

Charlie Jianzhong Zhang

Proceedings of the 25th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2024

Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Novel Quadratic Constraints for Extending LipSDP beyond Slope-Restricted Activations.

[BibT_eX]

[DOI]

Proceedings of the Twelfth International Conference on Learning Representations, 2024

LipSim: A Provably Robust Perceptual Similarity Metric.

[BibT_eX]

[DOI]

Sara Ghazanfari

Alexandre Araujo

Proceedings of the Twelfth International Conference on Learning Representations, 2024

Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization.

[BibT_eX]

[DOI]

Proceedings of the Twelfth International Conference on Learning Representations, 2024

On the (In)feasibility of ML Backdoor Detection as an Hypothesis Testing Problem.

[BibT_eX]

[DOI]

Georg Pichler

Marco Romanelli

Divya Prakash Manivannan

Proceedings of the International Conference on Artificial Intelligence and Statistics, 2024

SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs.

[BibT_eX]

[DOI]

Alhad Daftardar

Brandon Reagen

Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023

Lost at C: Data from the Security-focused User Study.

[BibT_eX]

[DOI]

Dataset, March, 2023

Optimizing the Use of Behavioral Locking for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Fairness via In-Processing in the Over-parameterized Regime: A Cautionary Tale with MinDiff Loss.

[BibT_eX]

[DOI]

Trans. Mach. Learn. Res., 2023

Differential Analysis of Triggers and Benign Features for Black-Box DNN Backdoor Detection.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2023

Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

AutoChip: Automating HDL Generation Using LLM Feedback.

[BibT_eX]

[DOI]

CoRR, 2023

Towards the Imagenets of ML4EDA.

[BibT_eX]

[DOI]

CoRR, 2023

Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT.

[BibT_eX]

[DOI]

CoRR, 2023

PriViT: Vision Transformers for Fast Private Inference.

[BibT_eX]

[DOI]

CoRR, 2023

R-LPIPS: An Adversarially Robust Perceptual Similarity Metric.

[BibT_eX]

[DOI]

Sara Ghazanfari

Alexandre Araujo

CoRR, 2023

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search.

[BibT_eX]

[DOI]

CoRR, 2023

Can deepfakes be created by novice users?

[BibT_eX]

[DOI]

CoRR, 2023

A Minimax Approach Against Multi-Armed Adversarial Attacks Detection.

[BibT_eX]

[DOI]

CoRR, 2023

Can Deepfakes be created on a whim?

[BibT_eX]

[DOI]

Proceedings of the Companion Proceedings of the ACM Web Conference 2023, 2023

Lost at C: A User Study on the Security Implications of Large Language Model Code Assistants.

[BibT_eX]

[DOI]

Proceedings of the 32nd USENIX Security Symposium, 2023

Towards better certified segmentation via diffusion models.

[BibT_eX]

[DOI]

Proceedings of the Uncertainty in Artificial Intelligence, 2023

Exploiting Connections between Lipschitz Structures for Certifiably Robust Deep Equilibrium Models.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Path Planning Under Uncertainty to Localize mmWave Sources.

[BibT_eX]

[DOI]

Kai Pfeiffer

Yuze Jia

Mingsheng Yin

Proceedings of the IEEE International Conference on Robotics and Automation, 2023

Invited Paper: Towards the Imagenets of ML4EDA.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Precoding-oriented Massive MIMO CSI Feedback Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2023

Benchmarking Large Language Models for Automated Verilog RTL Code Generation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Special Session: Machine Learning for Embedded System Design.

[BibT_eX]

[DOI]

Daniela Sanchez Lopera

Wolfgang Ecker

Jiang Hu

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

Characterizing and Optimizing End-to-End Systems for Private Inference.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Lost at C: Data from the Security-focused User Study.

[BibT_eX]

[DOI]

Dataset, October, 2022

Overriding Autonomous Driving Systems Using Adaptive Adversarial Billboards.

[BibT_eX]

[DOI]

Naman Patel

IEEE Trans. Intell. Transp. Syst., 2022

Robust Deep Learning for IC Test Problems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Millimeter Wave Wireless Assisted Robot Navigation With Link State Classification.

[BibT_eX]

[DOI]

Mingsheng Yin

IEEE Open J. Commun. Soc., 2022

Guest Editorial: Trustworthy AI.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Sphynx: A Deep Neural Network Design for Private Inference.

[BibT_eX]

[DOI]

IEEE Secur. Priv., 2022

An Upper Bound for the Distribution Overlap Index and Its Applications.

[BibT_eX]

[DOI]

CoRR, 2022

Security Implications of Large Language Model Code Assistants: A User Study.

[BibT_eX]

[DOI]

CoRR, 2022

Fairness via In-Processing in the Over-parameterized Regime: A Cautionary Tale.

[BibT_eX]

[DOI]

CoRR, 2022

Denial-of-Service Attacks on Learned Image Compression.

[BibT_eX]

[DOI]

CoRR, 2022

Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis.

[BibT_eX]

[DOI]

CoRR, 2022

A Feature-Based On-Line Detector to Remove Adversarial-Backdoors by Iterative Demarcation.

[BibT_eX]

[DOI]

IEEE Access, 2022

Feature Compression for Rate Constrained Object Detection on the Edge.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Multimedia Information Processing and Retrieval, 2022

Selective Network Linearization for Efficient Private Inference.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

High-level design methods for hardware security: is it the right choice? invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Locked Circuit Indistinguishability: A Notion of Security for Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE Computer Security Foundations Symposium, 2022

Protecting Hardware IP Cores During High-Level Synthesis.

[BibT_eX]

[DOI]

Behavioral Synthesis for Hardware Security, 2022

2021

ASSURE: RTL Locking Against an Untrusted Foundry.

[BibT_eX]

[DOI]

Christian Pilato

Donatella Sciuto

IEEE Trans. Very Large Scale Integr. Syst., 2021

Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks.

[BibT_eX]

[DOI]

Gaurav Rajavendra Reddy

Yiorgos Makris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Concentration of Measure Approach to Correlated Graph Matching.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Inf. Theory, 2021

Adversarially Robust Learning via Entropic Regularization.

[BibT_eX]

[DOI]

Gauri Jagatap

Ameya Joshi

Chinmay Hegde

Frontiers Artif. Intell., 2021

Guest Editors' Introduction: Competing to Secure SoCs.

[BibT_eX]

[DOI]

Jeyavijayan (JV) Rajendran

Daniel E. Holcomb

Ahmad-Reza Sadeghi

IEEE Des. Test, 2021

CryptoNite: Revealing the Pitfalls of End-to-End Private Inference at Scale.

[BibT_eX]

[DOI]

CoRR, 2021

Millimeter Wave Wireless-Assisted Robotic Navigation with Link State Classification.

[BibT_eX]

[DOI]

Mingsheng Yin

CoRR, 2021

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis.

[BibT_eX]

[DOI]

CoRR, 2021

Sphynx: ReLU-Efficient Network Design for Private Inference.

[BibT_eX]

[DOI]

CoRR, 2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2021

Special Section on Attacking and Protecting Artificial Intelligence.

[BibT_eX]

[DOI]

Shivam Bhasin

Francesco Regazzoni

CAAI Trans. Intell. Technol., 2021

Single-Shot Compression for Hypothesis Testing.

[BibT_eX]

[DOI]

Fabrizio Carpi

Proceedings of the 22nd IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2021

Circa: Stochastic ReLUs for Private Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles.

[BibT_eX]

[DOI]

Siva Kumar Sastry Hari

Iuri Frosio

Timothy Tsai

Alejandro J. Troccoli

Stephen W. Keckler

Anima Anandkumar

Proceedings of the IEEE Intelligent Vehicles Symposium, 2021

On Graph Matching Using Generalized Seed Side-Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2021

DeepReDuce: ReLU Reduction for Fast Private Inference.

[BibT_eX]

[DOI]

Proceedings of the 38th International Conference on Machine Learning, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks.

[BibT_eX]

[DOI]

Nimisha Limaye

Christian Pilato

Mohammed Thari Nabeel

Ozgur Sinanoglu

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

NNoculation: Catching BadNets in the Wild.

[BibT_eX]

[DOI]

Proceedings of the AISec@CCS 2021: Proceedings of the 14th ACM Workshop on Artificial Intelligence and Security, 2021

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Subverting Privacy-Preserving GANs: Hiding Secrets in Sanitized Images.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2020

The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication.

[BibT_eX]

[DOI]

Maria I. Mera Collantes

IEEE Embed. Syst. Lett., 2020

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Bait and Switch: Online Training Data Poisoning of Autonomous Driving Systems.

[BibT_eX]

[DOI]

Naman Patel

CoRR, 2020

Detecting Backdoors in Neural Networks Using Novel Feature-Based Anomaly Detection.

[BibT_eX]

[DOI]

CoRR, 2020

On Evaluating Neural Network Backdoor Defenses.

[BibT_eX]

[DOI]

CoRR, 2020

Adversarially Robust Learning via Entropic Regularization.

[BibT_eX]

[DOI]

Gauri Jagatap

Chinmay Hegde

CoRR, 2020

NNoculation: Broad Spectrum and Targeted Treatment of Backdoored DNNs.

[BibT_eX]

[DOI]

CoRR, 2020

On the Joint Typicality of Permutations of Sequences of Random Variables.

[BibT_eX]

[DOI]

CoRR, 2020

SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks.

[BibT_eX]

[DOI]

Maria I. Mera Collantes

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

CryptoNAS: Private Inference on a ReLU Budget.

[BibT_eX]

[DOI]

Brandon Reagen

Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

Model-Switching: Dealing with Fluctuating Workloads in Machine-Learning-as-a-Service Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th USENIX Workshop on Hot Topics in Cloud Computing, 2020

Anomaly Detection in Embedded Systems Using Power and Memory Side Channels.

[BibT_eX]

[DOI]

Jiho Park

Virinchi Roy Surabhi

Proceedings of the IEEE European Test Symposium, 2020

Is Register Transfer Level Locking Secure?

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

CompAct: On-chip <underline>Com</underline>pression of <underline>Act</underline>ivations for Low Power Systolic Array Based CNN Acceleration.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Split Manufacturing-Based Register Transfer-Level Obfuscation.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution.

[BibT_eX]

[DOI]

Kanad Basu

IEEE Des. Test, 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

CoRR, 2019

BadNets: Evaluating Backdooring Attacks on Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Concentration of Measure Approach to Database De-anonymization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Information Theory, 2019

Adaptive Adversarial Videos on Roadside Billboards: Dynamically Modifying Trajectories of Autonomous Vehicles.

[BibT_eX]

[DOI]

Naman Patel

Proceedings of the 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2019

TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities.

[BibT_eX]

[DOI]

Faiq Khalid

Muhammad Abdullah Hanif

Semeen Rehman

Theocharis Theocharides

Alessandro Artussi

Muthuramakrishnan Venkitasubramaniam

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2018

Outsourcing Private Machine Learning via Lightweight Secure Arithmetic Computation.

[BibT_eX]

[DOI]

CoRR, 2018

ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

CoRR, 2018

Chapter Five - Dynamic Power Management for Dark Silicon Multicore Processors☆.

[BibT_eX]

[DOI]

Adv. Comput., 2018

Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Special session: Recent developments in hardware security.

[BibT_eX]

[DOI]

Ro Cammarota

Naghmeh Karimi

Jeyavijayan Rajendran

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Fine-Pruning: Defending Against Backdooring Attacks on Deep Neural Networks.

[BibT_eX]

[DOI]

Brendan Dolan-Gavitt

Proceedings of the Research in Attacks, Intrusions, and Defenses, 2018

Optimal Active social Network De-anonymization Using Information Thresholds.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

Typicality Matching for Pairs of Correlated Graphs.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

FATE: fast and accurate timing error prediction framework for low power DNN accelerator design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

TAO: techniques for algorithm-level obfuscation during high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Matching Graphs with Community Structure: A Concentration of Measure Approach.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Allerton Conference on Communication, 2018

2017

Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Guest Editors' Introduction: Computing in the Dark Silicon Era.

[BibT_eX]

[DOI]

Vikas Chandra

IEEE Des. Test, 2017

Computing in the Dark Silicon Era: Current Trends and Research Challenges.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access.

[BibT_eX]

[DOI]

Mahesh Tripunitara

CoRR, 2017

BadNets: Identifying Vulnerabilities in the Machine Learning Model Supply Chain.

[BibT_eX]

[DOI]

Tianyu Gu

Brendan Dolan-Gavitt

CoRR, 2017

Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism.

[BibT_eX]

[DOI]

Jun Zhang

CoRR, 2017

IoT-enabled Distributed Cyber-attacks on Transmission and Distribution Grids.

[BibT_eX]

[DOI]

Yury Dvorkin

CoRR, 2017

SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud.

[BibT_eX]

[DOI]

Tianyu Gu

Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Reverse engineering camouflaged sequential circuits without scan access.

[BibT_eX]

[DOI]

Mahesh Tripunitara

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Optimal checkpointing for secure intermittently-powered IoT devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

The Need for Declarative Properties in Digital IC Security.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

BandiTS: Dynamic timing speculation using multi-armed bandit based optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Inspiring trust in outsourced integrated circuit fabrication.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An information theoretic framework for active de-anonymization in social networks based on group memberships.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Allerton Conference on Communication, 2017

Seeded graph matching: Efficient algorithms and theoretical guarantees.

[BibT_eX]

[DOI]

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Energy Storage and Regulation: An Analysis.

[BibT_eX]

[DOI]

Dariush Fooladivanda

Catherine Rosenberg

IEEE Trans. Smart Grid, 2016

Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Fragility of the commons under prospect-theoretic risk attitudes.

[BibT_eX]

[DOI]

Ashish Ranjan Hota

Shreyas Sundaram

Games Econ. Behav., 2016

Variability and Reliability Awareness in the Age of Dark Silicon.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Thread Progress Equalization: Dynamically Adaptive Power and Performance Optimization of Multi-threaded Applications.

[BibT_eX]

[DOI]

CoRR, 2016

Non-Deterministic Timers for Hardware Trojan Activation (or How a Little Randomness Can Go the Wrong Way).

[BibT_eX]

[DOI]

Frank Imeson

Saeed Nejati

Proceedings of the 10th USENIX Workshop on Offensive Technologies, 2016

Optimal de-anonymization in random graphs with community structure.

[BibT_eX]

[DOI]

Efe Onaran

Proceedings of the 37th IEEE Sarnoff Symposium 2016, Newark, NJ, USA, 2016

Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks.

[BibT_eX]

[DOI]

Maria I. Mera Collantes

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Power-aware virtual machine mapping in the data-center-on-a-chip paradigm.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Can flexible, domain specific programmable logic prevent IP theft?

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Synergistic timing speculation for multi-threaded programs.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Verifiable ASICs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Analysis of energy- and SoC-neutral contracts for frequency regulation with energy storage.

[BibT_eX]

[DOI]

Dariush Fooladivanda

Catherine Rosenberg

Proceedings of the 2015 IEEE International Conference on Smart Grid Communications, 2015

Dark Silicon: From Computation to Communication.

[BibT_eX]

[DOI]

Jörg Henkel

Haseeb Bokhari

Muhammad Usman Karim Khan

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes.

[BibT_eX]

[DOI]

Proceedings of the 22nd Annual Network and Distributed System Security Symposium, 2015

Energy efficient scheduling for web search on heterogeneous microservers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient computing from systems-on-chip to micro-server and data centers.

[BibT_eX]

[DOI]

Paul Bogdan

Ümit Y. Ogras

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Variability-aware dark silicon management in on-chip many-core systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors.

[BibT_eX]

[DOI]

Da-Cheng Juan

ACM Trans. Design Autom. Electr. Syst., 2014

Reliable Computing with Ultra-Reduced Instruction Set Coprocessors.

[BibT_eX]

[DOI]

Dan Wang

Aravindkumar Rajendiran

IEEE Micro, 2014

State of Charge Evolution Equations for Flywheels.

[BibT_eX]

[DOI]

CoRR, 2014

An analysis of energy storage and regulation.

[BibT_eX]

[DOI]

Dariush Fooladivanda

Catherine Rosenberg

Proceedings of the 2014 IEEE International Conference on Smart Grid Communications, 2014

Shielding and securing integrated circuits with sensors.

[BibT_eX]

[DOI]

Davood Shahrjerdi

Jeyavijayan Rajendran

Farinaz Koushanfar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Dark silicon as a challenge for hardware/software co-design.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era.

[BibT_eX]

[DOI]

Bharathwaj Raghunathan

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Addressing Process Variations at the Microarchitecture and System Level.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2013

A Hybrid Amplitude/Time Encoding Scheme for Enhancing Coding Efficiency and Dynamic Range in Digitally Modulated Power Amplifiers.

[BibT_eX]

[DOI]

Peter Jingjing Xia

Slim Boumaiza

IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design.

[BibT_eX]

[DOI]

Amr M. S. Tosson

Mohab H. Anis

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation.

[BibT_eX]

[DOI]

Frank Imeson

Ariq Emtenan

Proceedings of the 22th USENIX Security Symposium, Washington, DC, USA, August 14-16, 2013, 2013

Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements.

[BibT_eX]

[DOI]

Conor O'Sullivan

Peter M. Levine

Proceedings of the International Symposium on Quality Electronic Design, 2013

Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions.

[BibT_eX]

[DOI]

Da-Cheng Juan

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors.

[BibT_eX]

[DOI]

Bharathwaj Raghunathan

Yatish Turakhia

Proceedings of the Design, Automation and Test in Europe, 2013

Low cost permanent fault detection using ultra-reduced instruction set co-processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors.

[BibT_eX]

[DOI]

Yatish Turakhia

Bharathwaj Raghunathan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Resource sharing games with failures and heterogeneous risk attitudes.

[BibT_eX]

[DOI]

Ashish Ranjan Hota

Shreyas Sundaram

Proceedings of the 51st Annual Allerton Conference on Communication, 2013

2012

Exploiting Process Variability in Voltage/Frequency Control.

[BibT_eX]

[DOI]

Sebastian Herbert

IEEE Trans. Very Large Scale Integr. Syst., 2012

System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

Radu Marculescu

ACM J. Emerg. Technol. Comput. Syst., 2012

Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms.

[BibT_eX]

[DOI]

Chirag Ravishankar

Andrew A. Kennings

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip.

[BibT_eX]

[DOI]

Chirag Ravishankar

Andrew A. Kennings

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only).

[BibT_eX]

[DOI]

Chirag Ravishankar

Andrew A. Kennings

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Reliable computing with ultra-reduced instruction set co-processors.

[BibT_eX]

[DOI]

Aravindkumar Rajendiran

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Robust heterogeneous data center design: a principled approach.

[BibT_eX]

[DOI]

Shreyas Sundaram

SIGMETRICS Perform. Evaluation Rev., 2011

Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations.

[BibT_eX]

[DOI]

Da-Cheng Juan

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Custom feedback control: enabling truly scalable on-chip power management for MPSoCs.

[BibT_eX]

[DOI]

Radu Marculescu

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Process variation aware performance modeling and dynamic power management for multi-core systems.

[BibT_eX]

[DOI]

Sebastian Herbert

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

System-level process variability analysis and mitigation for 3D MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

System-level throughput analysis for process variation aware multiple voltage-frequency island designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Voting-based active contour segmentation of fMRI images of the brain.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

System-level mitigation of WID leakage power variability using body-bias islands.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007

Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

System-level process-driven variability analysis for single and multiple voltage-frequency island systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2004

Static Transition Probability Analysis Under Uncertainty.

[BibT_eX]

[DOI]