Sid Ahmed Ali Touati

IEEE Trans. Multi Scale Comput. Syst., 2018

2016

Going beyond Mean and Median Programs Performances.

[BibT_eX]

[DOI]

Julien Worms

Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2013

How to eliminate non-positive circuits in periodic scheduling: a proactive strategy based on shortest path equations.

[BibT_eX]

[DOI]

Sébastien Briais

RAIRO Oper. Res., 2013

Minimal Unroll Factor for Code Generation of Software Pipelining.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2013

The Speedup-Test: a statistical methodology for programme speedup analysis and computation.

[BibT_eX]

[DOI]

Julien Worms

Sébastien Briais

Concurr. Comput. Pract. Exp., 2013

Dynamic Thread Pinning for Phase-Based OpenMP Programs.

[BibT_eX]

[DOI]

Abdelhafid Mazouz

Proceedings of the Euro-Par 2013 Parallel Processing, 2013

2012

On the effectiveness of register moves to minimise post-pass unrolling in software pipelined loops.

[BibT_eX]

[DOI]

Mounira Bachir

Albert Cohen

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

2011

Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors.

[BibT_eX]

[DOI]

Frederic Brault

Benoît Dupont de Dinechin

ACM Trans. Embed. Comput. Syst., 2011

Evaluating address register assignment and offset assignment algorithms.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2011

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling.

[BibT_eX]

[DOI]

Sébastien Briais

J. Comb. Optim., 2011

Performance evaluation and analysis of thread pinning strategies on multi-core platforms: Case study of SPEC OMP applications on intel architectures.

[BibT_eX]

[DOI]

Abdelhafid Mazouz

Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Loop unrolling minimisation in the presence of multiple register types: A viable alternative to modulo variable expansion.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

2010

FADAlib: an open source C++ library for fuzzy array dataflow analysis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computational Science, 2010

Study of Variations of Native Program Execution Times on Multi-Core Architectures.

[BibT_eX]

[DOI]

Abdelhafid Mazouz

Proceedings of the CISIS 2010, 2010

Méthodes d'optimisations de programmes bas niveau. (On Backend Code Optimisation Methods).

[BibT_eX]

[DOI]

, 2010

2009

Periodic register saturation in innermost loops.

[BibT_eX]

[DOI]

Zsolt Mathe

Parallel Comput., 2009

Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops.

[BibT_eX]

[DOI]

Mounira Bachir

David Gregg

Proceedings of the Languages and Compilers for Parallel Computing, 2009

On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.

[BibT_eX]

[DOI]

Samir Ammenouche

William Jalby

Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009

2008

Post-pass periodic register allocation to minimise loop unrolling degree.

[BibT_eX]

[DOI]

Mounira Bachir

Albert Cohen

Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Optimization and Applications, 2008

2007

On the Periodic Register Need in Software Pipelining.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Code-size conscious pipelining of imperfectly nested loops.

[BibT_eX]

[DOI]

Mohammed Fellahi

Albert Cohen

Proceedings of the 2007 workshop on MEmory performance, 2007

Evaluation of Offset Assignment Heuristics.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2006

An efficient memory operations optimization technique for vector loops on Itanium 2 processors.

[BibT_eX]

[DOI]

William Jalby

Christophe Lemuet

Concurr. Comput. Pract. Exp., 2006

On the decidability of phase ordering problem in optimizing compilation.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

2005

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2005

2004

Early Periodic Register Allocation on ILP Processors.

[BibT_eX]

[DOI]

Christine Eisenbeis

Parallel Process. Lett., 2004

On the Optimality of Register Saturation.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Workshop on Compiler Optimization Meets Compiler Verification, 2004

Improving Load/Store Queues Usage in Scientific Computing.

[BibT_eX]

[DOI]

Christophe Lemuet

William Jalby

Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

2003

Early Control of Register Pressure for Software Pipelined Loops.

[BibT_eX]

[DOI]

Christine Eisenbeis

Proceedings of the Compiler Construction, 12th International Conference, 2003

2002

[BibT_eX]

, 2002

[BibT_eX]

[DOI]

PhD thesis, 2002

2001

Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

[BibT_eX]

[DOI]

Proceedings of the Compiler Construction, 10th International Conference, 2001

2000

Load-store optimization for software pipelining.

[BibT_eX]

[DOI]

Min Dai

Christine Eisenbeis