Siavoosh Payandeh Azad
Orcid: 0000-0001-9177-7779
According to our database1,
Siavoosh Payandeh Azad
authored at least 29 papers
between 2014 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
2014
2015
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2017
2018
2019
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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Bibliography
2019
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the Computational Science - ICCS 2019, 2019
Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the IEEE International Conference on Automation, 2018
2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Comprehensive performance and robustness analysis of 2D turn models for network-on-chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
From online fault detection to fault management in Network-on-Chips: A ground-up approach.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
2016
CoRR, 2016
SoCDep<sup>2</sup>: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Digital system modeling and synthesis as an introduction to Computer Systems Engineering.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014