Siang-Yun Lee

According to our database, Siang-Yun Lee authored at least 17 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers.

Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025

Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron.

Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

2024

Technology-Aware Logic Synthesis for Superconducting Electronics.

Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration.

Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization.

Siang-Yun Lee, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions.

Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli

CoRR, 2023

2022

A Simulation-Guided Paradigm for Logic Synthesis and Verification.

Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.

Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

CoRR, 2022

Majority-based Design Flow for AQFP Superconducting Family.

Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Beyond local optimality of buffer and splitter insertion for AQFP circuits.

Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.

Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.

Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

CoRR, 2021

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.

Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.

Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Simulation-Guided Boolean Resubstitution.

Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli

CoRR, 2020

2019

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks.

Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

Canonicalization of threshold logic representation and its applications.

Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the International Conference on Computer-Aided Design, 2018